Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-25
2010-06-08
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C430S005000
Reexamination Certificate
active
07735054
ABSTRACT:
This invention discloses a photomask manufacturing method. A pattern dimensional map is generated by preparing a photomask in which a mask pattern is formed on a transparent substrate, and measuring a mask in-plane distribution of the pattern dimensions. A transmittance correction coefficient map is generated by dividing a pattern formation region into a plurality of subregions, and determining a transmittance correction coefficient for each of the plurality of subregions. The transmittance correction value of each subregion is calculated on the basis of the pattern dimensional map and the transmittance correction coefficient map. The transmittance of the transparent substrate corresponding to each subregion is changed on the basis of the transmittance correction value.
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Notice of Reasons for Rejection mailed from the Japanese Patent Office, Jun. 26, 2008, for Application No. 2006-202385.
Japanese Patent Office's Decision of Rejection mailed Sep. 16, 2008.
Fukuhara Kazuya
Hirano Takashi
Itoh Masamitsu
Chiang Jack
Dimyan Magid Y
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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