Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-02-16
2003-05-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06560737
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and circuitry for adding scan controllability and observability to Domino CMOS logic or other logic gates.
BACKGROUND OF THE INVENTION
Scan control circuitry is used for testing of logic gates. Using the scan control circuitry, logic bits are scanned into the circuitry using one or more normal clock steps, and the results are observed. Typical scanning circuitry often requires a large overhead in terms of the number of transistors that must be added to test particular logic circuitry, such as Domino CMOS logic gates. The scan circuitry can also generate inherent races that can be difficult to control. In addition, the circuitry often must be specially modified for different types of logic cells. Accordingly, a need exists for improved scan circuitry for testing and observing operation of Domino CMOS logic or other types of logic gates.
SUMMARY OF THE INVENTION
A circuit consistent with the present invention is used for scanning a logic gate in order to observe operation of the logic gate. It includes a master scan stage for scanning a bit into a first logic cell, and the master scan stage uses a latch structure in the first logic cell for scanning the bit. The circuit also includes a slave scan stage for scanning the bit from the first logic cell into a second logic cell.
A method consistent with the present invention includes master and slave scanning steps. The master scanning step includes scanning a bit into a master scan stage having a first logic cell. It further includes using a latch structure in the first logic cell for scanning the bit and receiving clock signals for controlling the scanning. The slave scanning step includes scanning the bit from the first logic cell into a slave scan stage having a second logic cell.
REFERENCES:
patent: 5517136 (1996-05-01), Harris et al.
patent: 5619511 (1997-04-01), Sugisaw a et al.
patent: 5740181 (1998-04-01), Heikes et al.
patent: 5764083 (1998-06-01), Nguyen et al.
patent: 5796282 (1998-08-01), Sprague et al.
patent: 5825208 (1998-10-01), Levy et al.
patent: 5859999 (1999-01-01), Morris et al.
patent: 5860017 (1999-01-01), Sharangpani et al.
patent: 5938782 (1999-08-01), Kay
patent: 6198324 (2001-03-01), Schober
Wolfe, A., “Patents shed light on Merced's Innards”, Electronic Engineering Times, Feb. 15, 1999.
Arnold Barry J
Colon-Bonet Glenn T
Naffziger Samuel D
Sullivan Thomas Justin
Chase Shelly A
De'cady Albert
Hewlett--Packard Development Company, L.P.
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