Method for achieving global planarization by forming minimum mes

Details Method for achieving global planarization by forming minimum mes Method for achieving global planarization by forming minimum mes

1997-09-04

1999-07-20

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438424, 438427, 438435, 438692, H01L 21336

Patent

active

059267135

ABSTRACT:
An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of silicon risers formed in wide isolation regions. The space between silicon risers are ideally suited for optimal fill of a dielectric deposited across the semiconductor topography, i.e., across and between the silicon risers formed between active areas. The silicon risers, and optimally dimensioned trenches extending between the risers, enhance the planarity of the deposited dielectric. The deposited dielectric upper surface includes recesses of minimal elevational disparity, wherein the recesses are closely spaced in alignment directly above the trenches formed between silicon risers. The recesses can be readily removed by a chemical-mechanical polishing step with minimal deformity to the polishing pad, resulting in global planarization of the dielectric upper surface.

REFERENCES:
patent: 4211582 (1980-07-01), Horng et al.
patent: 4274909 (1981-06-01), Venkataraman et al.
patent: 4385975 (1983-05-01), Chu et al.
patent: 4390393 (1983-06-01), Ghezzo et al.
patent: 4445967 (1984-05-01), Kameyama
patent: 4532701 (1985-08-01), Kameyama et al.
patent: 4671970 (1987-06-01), Keiser et al.
patent: 4868136 (1989-09-01), Ravaglia
patent: 4871685 (1989-10-01), Taka et al.
patent: 4873203 (1989-10-01), Kaga et al.
patent: 4906585 (1990-03-01), Neppl et al.
patent: 4952524 (1990-08-01), Lee et al.
patent: 4980311 (1990-12-01), Namose
patent: 4994406 (1991-02-01), Vasquez et al.
patent: 5004703 (1991-04-01), Zdebel et al.
patent: 5011788 (1991-04-01), Kawaji et al.
patent: 5096848 (1992-03-01), Kawamura
patent: 5175122 (1992-12-01), Wang et al.
patent: 5225358 (1993-07-01), Pasch
patent: 5229315 (1993-07-01), Jun et al.
patent: 5229316 (1993-07-01), Lee
patent: 5231046 (1993-07-01), Tasaka
patent: 5292689 (1994-03-01), Cronin et al.
patent: 5294562 (1994-03-01), Lur et al.
patent: 5308784 (1994-05-01), Kim et al.
patent: 5308786 (1994-05-01), Lur et al.
patent: 5371036 (1994-12-01), Lur et al.
patent: 5372950 (1994-12-01), Kim et al.
patent: 5372968 (1994-12-01), Lur et al.
patent: 5691252 (1997-11-01), Pan
patent: 5696020 (1997-12-01), Ryum et al.
IBM Technical Disclosure Bulletin, "Forming Wide Trench Dielectric Isolation", Apr. 1983, 2 pages.
Written Opinion for PCT/US97/02438 dated Jan. 15, 1998.
International Search Report for PCT/US 97/03255 dated Jul. 4, 1997.
International Search Report for PCT/US 97/02438 dated Jun. 4, 1997.
Wolf; "Silicon Processing for the VLSI Era, vol. 1: Process Technology", Lattice Press; 1986; pp. 407-458.

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