Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-27
2008-03-04
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07340700
ABSTRACT:
A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.
REFERENCES:
patent: 6775779 (2004-08-01), England et al.
patent: 7155693 (2006-12-01), Rodman
patent: 2003/0115562 (2003-06-01), Martin et al.
patent: 2003/0145297 (2003-07-01), Cote et al.
patent: 2004/0045015 (2004-03-01), Haji-Aghajani et al.
patent: 2004/0254755 (2004-12-01), Byrn et al.
patent: 2005/0144585 (2005-06-01), Daw et al.
patent: 2005/0198597 (2005-09-01), Zhu et al.
patent: 2006/0036972 (2006-02-01), Barbera et al.
patent: 2006/0259884 (2006-11-01), Fong et al.
patent: 2006/0271890 (2006-11-01), Hekmatpour et al.
F. Fernandes et al.; “A Probabilistic Method for the Computation of Testability of RTL Constructs,”Design, Automation and Test in Europe conference and Exhibition, vol. 1, 2004, Paris, France, pp. 10176-10181.
M.B. Santos et al.; “RTL Test Pattern Generation for High Quality Loosely Deterministic BIST,”Design, Automation and Test in Europe Conference and Exhibition, 2003, Munich, Germany, 10994-10999.
A. Krstic et al.; “Embedded Software-Based Self-Test for Programmable Core-Based Designs,”IEEE Design & Test of Computers, 2002, pp. 18-27.
Y. Zorian.; “Embedded Test complicates SoC Realm,”EE Times, article, Dec. 2000.
A. Sehgal. et al.; “IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores,” IEEE Transactions International Test Conference, 2004, pp. 1203-1212.
V. Iyengar et al.; “Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip,”Journal of Electronic Testing: Theory and Applications 18, 2002, pp. 213-230.
D. Cassell.; “A Randomization-test Wrapper for SAS® PROCs,” Paper 251-27, pp. 1-4, 2002.
M. Ricchetti.; “Overview the Proposed IEEE P1500 Scaleable Architecture for Testing Embedded Cores,” IEEE P1500 Architecture Task Force, 1999, pp. 1-13.
R. Dorsch et al.; Adapting an SoC to ATE Concurrent Test Capabilities,IEEE International Test Conference, 2002, pp. 1169-1175.
Mourani, M. & Papachristou, C.; “An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing,” 2000.
Byrn Jonathan
Emerson Steven
Gabrielson Donald
Lippert Gary
Chiang Jack
LSI Logic Corporation
Memula Suresh
Westman Champlin & Ke
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