Method for a self-aligned select gate for a split-gate flash mem

Details Method for a self-aligned select gate for a split-gate flash mem Method for a self-aligned select gate for a split-gate flash mem

1999-04-29

2000-06-06

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438366, H01L 21336

Patent

active

060717777

ABSTRACT:
A process for making a self-aligned select gate for a split-gate flash memory structure uses a patterned nitride layer and a photoresist layer to serve as masks to define a select gate length, facilitates a self-aligned ion implantation to form a drain region of a memory cell, and defines a distance between the select gate and the drain region.

REFERENCES:
patent: 5242848 (1993-09-01), Yeh
patent: 5702965 (1997-12-01), Kim
patent: 5970371 (1999-10-01), Hsieh et al.
patent: 6001690 (1999-12-01), Chien et al.

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