Method fabricating metal interconnected structure

Details Method fabricating metal interconnected structure Method fabricating metal interconnected structure

1999-01-26

2001-01-02

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S653000

Utility Patent

active

06169028

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a semiconductor fabrication method, and more particularly to fabrication of a metal interconnect in which a chemical mechanical polishing (CMP) technique, customarily referred to as Cu-CMP, is required to polish a copper-based metallization layer to form the interconnect.
2. Description of the Related Art
High-density integrated circuits, such as very large scale integration (VLSI) ICs, are typically formed with a multi-level interconnect structure including two or more levels of metal-interconnect structures that serve as wiring line structures for electrically interconnecting the various components in the integrated circuits. A multi level interconnect structure includes a first layer (base layer) of metal-interconnect structure which is electrically connected to the source/drain regions of the MOS transistors formed in the integrated circuit, and at least a second layer of metal-interconnect structure which is separated from the base layer of metal-interconnect structure by an insulating layer, with the second layer of a metal-interconnect structure being electrically connected to the base layer of a metal-interconnect structure via metal plug (also called a via) formed in the insulating layer. Still another or several more layers of metal layers of metal-interconnect structures can be formed over the second layer of the metal-interconnect structure to constitute the multi-level interconnect structure.
One drawback to the conventional multi-level interconnect structure, however, is that when the IC device is further scaled down, the structure causes an increase in the capacitive effect between neighboring metal lines, thus increasing the resistance-capacitance (RC) delay and cross talk in the metal plugs. As a consequence, the transmission of the data through the metal lines in the metal-interconnect structures is slowed, thus degrading the performance of the IC device.
Copper, which has a low electrical resistance, is presently being experimented with in metal-interconnect structure formation in integrated circuits to provide increased conductivity to the data transmission lines in the integrated circuit. A conventional process for fabricating a metal-interconnect structure is depicted in the following with reference to FIGS.
1
A-
1
C.
Referring to
FIG. 1A
, a semiconductor substrate
10
is provided. The substrate
10
includes a conductive layer, such as a source/drain region or other conductive elements. An intermetal dielectric layer
12
is formed on the substrate
10
. A dual damascene opening
14
, which comprises a via and a trench, is formed in the intermetal dielectric layer
12
. Furthermore, a trench
16
is found in the intermetal dielectric layer
12
. The trench
16
is larger than the dual damascene opening
14
.
Referring to
FIG. 1B
, a conformal tantalum nitride layer
18
is formed on the intermetal dielectric layer
12
to partially fill the dual damascene opening
14
and the large trench
16
. A copper layer
20
is formed on the tantalum nitride layer
18
and overflows the dual damascene opening
14
and the large trench
16
. The tantalum nitride layer
18
is used to enhance the adhesion between the copper layer
20
and the intermetal dielectric layer
12
.
Referring to
FIG. 1C
, a chemical mechanical polishing process is performed to form a dual damascene
20
a
and the copper plug
20
b
in the trench
16
. The tantalum layer
18
is harder than the copper layer
20
. A part of the copper layer
20
positioned in the trench
16
exposes a larger area than other regions so that the top surface of the copper plug
20
b
has a dishing shape as shown in figure. The dishing shape makes the overall top surface of the wafer highly non-planar, and therefore may cause the subsequently deposited insulating oxide layers to be poor in planarization. This may cause erosion to the oxide layers, resulting in an increase in the resistance of the metal-interconnect structure, thus degrading the performance of the resultant IC device.
One conventional solution to the forgoing problem is to use multiple polishing steps with various kinds of slurry and different polish pads to reduce the undesired high CMP selectivity between the copper-based metal-interconnect structure and the barrier layer. However, this practice will significantly increase the number of reworks of the CMP process, making the overall process very complex and thus costly to implement.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method for fabricating a metal interconnect structure in an integrated circuit, which can be utilized in the fabrication of a copper-based interconnect structure to prevent the undesired dishing of the copper-based interconnect structure due to high CMP selectivity between copper and the barrier layer, so as to make the copper-based interconnect structure high in resistance and planarization.
The invention achieves the above-identified objects by providing a method for fabricating a metal interconnect structure. A semiconductor substrate comprising a conductive layer therein is provided. A dielectric layer is formed on the semiconductor substrate. A part of the dielectric layer is removed to form a dual damascene opening and a trench therein, wherein the dual damascene opening exposes the conductive layer. The trench is larger than the dual damascene opening. A conformal barrier layer is formed on the dielectric layer. A conformal metal layer is formed on the barrier layer to fill the dual damascene opening and to partially fill the trench. The metal layer positioned in the trench has a thickness equal to the depth of the trench. A conformal cap layer is formed on the metal layer. A CMP process is performed to remove the cap layer, the metal layer and the barrier layer out from the trench and out from the dual damascene opening.


REFERENCES:
patent: 5604156 (1997-02-01), Chung et al.
patent: 5814557 (1999-09-01), Venkatraman et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 6001730 (1999-12-01), Farkas et al.

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