Method, architecture and circuit for writing to and reading from

Details Method, architecture and circuit for writing to and reading from Method, architecture and circuit for writing to and reading from

1998-06-29

2000-09-19

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523006, 36523008, 3652335, G11C 700

Patent

active

061222038

ABSTRACT:
A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) an enable signal and (ii) a detect signal.

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