Method, architecture and circuit for writing to and reading from

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36523006, 36523008, 3652335, G11C 700

Patent

active

061222038

ABSTRACT:
A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) an enable signal and (ii) a detect signal.

REFERENCES:
patent: 4825416 (1989-04-01), Tam et al.
patent: 5058076 (1991-10-01), Kiuchi
patent: 5193076 (1993-03-01), Houston
patent: 5291447 (1994-03-01), Kodama et al.
patent: 5309395 (1994-05-01), Dickinson et al.
patent: 5325337 (1994-06-01), Buttar
patent: 5388075 (1995-02-01), Vinal
patent: 5394361 (1995-02-01), Dickinson
patent: 5473565 (1995-12-01), Kusakari
patent: 5473568 (1995-12-01), Okamura
patent: 5479374 (1995-12-01), Kobayashi et al.
patent: 5502672 (1996-03-01), Kwon
patent: 5502681 (1996-03-01), Park
patent: 5544101 (1996-08-01), Houston
patent: 5559752 (1996-09-01), Stephens, Jr. et al.
patent: 5568073 (1996-10-01), McClure
patent: 5596539 (1997-01-01), Passow et al.
patent: 5604705 (1997-02-01), Ackland et al.
patent: 5610862 (1997-03-01), Teel
patent: 5625595 (1997-04-01), Ikeda
patent: 5631866 (1997-05-01), Oka et al.
patent: 5644773 (1997-07-01), DiMarco
patent: 5652724 (1997-07-01), Manning
patent: 5659513 (1997-08-01), Hirose et al.
patent: 5661417 (1997-08-01), Kondoh
patent: 5661691 (1997-08-01), Lin
patent: 5666321 (1997-09-01), Schaefer
patent: 5703831 (1997-12-01), Sawada
patent: 5717653 (1998-02-01), Suzuki
patent: 5724287 (1998-03-01), Takenaka
patent: 5729503 (1998-03-01), Manning
patent: 5742552 (1998-04-01), Greenberg
patent: 5745419 (1998-04-01), Brauch
patent: 5748544 (1998-05-01), Hashimoto
patent: 5751170 (1998-05-01), Pyeon
patent: 5751647 (1998-05-01), O'Toole
patent: 5752270 (1998-05-01), Wada
patent: 5754481 (1998-05-01), Yabe et al.
patent: 5757718 (1998-05-01), Suzuki
patent: 5761136 (1998-06-01), Park et al.
patent: 5778440 (1998-07-01), Yiu et al.
patent: 5822254 (1998-10-01), Koshikawa et al.
patent: 5896319 (1999-04-01), Takehana
patent: 5986970 (1999-11-01), Hunt et al.
Jeffrey S. Hunt et al., U.S.S.N. 09/106,806 Method, Architecture and Circuit for Writing to a Memory, filed Jun. 29, 1998.
Jeffrey S. Hunt et al., U.S.S.N. 09/132,100 Method, Architecture and Circuit for Reducing and/or Eliminating Small Signal Voltage Swing Sensitivity, filed Aug. 10, 1998.
Satish Saripella et al., U.S.S.N. 09/126,832 Wordline Synchronized Reference Voltage Generator, filed Jul. 31, 1998.
Jeffrey S. Hunt et al., U.S.S.N. 09/103,960 Self-Timed Sense Amplifier Evaluation Scheme, filed Jun. 24, 1998.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method, architecture and circuit for writing to and reading from does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method, architecture and circuit for writing to and reading from, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, architecture and circuit for writing to and reading from will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1079984

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.