Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-05-03
2008-09-02
Bataille, Pierre Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S217000, C712S207000
Reexamination Certificate
active
07421540
ABSTRACT:
A mechanism is provided that identifies instructions that access storage and may be candidates for cache prefetching. The mechanism augments these instructions so that any given instance of the instruction operates in one of four modes, namely normal, unexecuted, data gathering, and validation. In the normal mode, the instruction merely performs the function specified in the software runtime environment. An instruction in unexecuted mode, upon the next execution, is placed in data gathering mode. When an instruction in the data gathering mode is encountered, the mechanism of the present invention collects data to discover potential fixed storage access patterns. When an instruction is in validation mode, the mechanism of the present invention validates the presumed fixed storage access patterns.
REFERENCES:
patent: 5704053 (1997-12-01), Santhanam
patent: 5805863 (1998-09-01), Chang
patent: 5854934 (1998-12-01), Hsu et al.
patent: 5933643 (1999-08-01), Holler
patent: 6321330 (2001-11-01), Doshi et al.
patent: 6453389 (2002-09-01), Weinberger et al.
patent: 6546550 (2003-04-01), Ogata et al.
patent: 6634024 (2003-10-01), Tirumalai et al.
patent: 6701334 (2004-03-01), Ye et al.
patent: 6961930 (2005-11-01), Waldspurger et al.
patent: 2003/0088863 (2003-05-01), Tirumalai et al.
patent: 2003/0088864 (2003-05-01), Tirumalai et al.
patent: 2003/0126591 (2003-07-01), Wu et al.
patent: 2003/0145314 (2003-07-01), Nguyen et al.
patent: 2003/0196046 (2003-10-01), Abdallah et al.
patent: 2003/0204840 (2003-10-01), Wu
patent: 2004/0031026 (2004-02-01), Srinivasan
patent: 2004/0117557 (2004-06-01), Paulraj et al.
patent: 2004/0194077 (2004-09-01), Bharadwaj et al.
patent: 2004/0243981 (2004-12-01), Luk et al.
Inagaki et al., “Stride Prefetching by Dynamically Inspecting Objects”, SIGPLAN Not. (USA) vol. 38, No. 5, May 2003, abstract.
Van den berg J., et al., “The Loop Compiler for Java and JML”, Tools and Algorithms for the Construction and Analysis of Systems, Apr. 2-6, 2001, vol. 2031; p. 229-312.
Donawa Christopher Michael
Kielstra Allan Henry
Bataille Pierre Michel
Glanzman Gerald H.
International Business Machines - Corporation
Schnee Hal
Talpis Matthew
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