Method, apparatus and computer program product for designing...

Details Method, apparatus and computer program product for designing... Method, apparatus and computer program product for designing...

2005-07-28

2009-06-02

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07543204

ABSTRACT:
Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.

REFERENCES:
patent: 5280616 (1994-01-01), Butler et al.
patent: 6002633 (1999-12-01), Oppold et al.
patent: 6028983 (2000-02-01), Jaber
patent: 6106568 (2000-08-01), Beausang et al.
patent: 6448835 (2002-09-01), Douskey et al.
patent: 6651197 (2003-11-01), Wildes et al.
patent: 6970815 (2005-11-01), Bombal et al.
patent: 7231563 (2007-06-01), Vinke et al.
patent: 2005/0028060 (2005-02-01), Dervisoglu et al.

Affiliated with

Also associated with

Rating

Method, apparatus and computer program product for designing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method, apparatus and computer program product for designing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, apparatus and computer program product for designing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4086789