Method and test site to monitor alignment shift and buried conta

Details Method and test site to monitor alignment shift and buried conta Method and test site to monitor alignment shift and buried conta

1998-12-17

1999-09-21

Bowers, Charles

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

438 14, 438 22, 257 48, G01R 2714, G01R 3126

Patent

active

059565667

ABSTRACT:
A method and test site for monitoring the extent of buried contact trench formation in MOS FET integrated circuit wafers is described. A number of doped silicon parallel first test electrodes are formed in test site regions of a wafer and connected in series. The test site regions are located in the spaces between chip regions of the wafer. A layer of gate oxide is then deposited over the wafer. Test openings over the first test electrodes and buried contact openings are etched in the gate oxide layer at the same time. The test openings have the same size and shape as the buried contact openings. After polysilicon and metal silicide is deposited a photoresist mask is formed to etch the buried contact electrodes, the gate electrodes, and second test electrodes which are located directly above the test openings. Any misalignment in the photoresist mask will cause trenches to be formed in the first test electrodes as well as the formation of buried contact trenches. These trenches in the first test electrodes will cause an increase the resistance of the first test electrodes which is related to the extent of the buried contact trenches. The first test electrodes can be oriented to measure the extent of buried contact trench formation regardless of orientation.

REFERENCES:
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patent: 5629772 (1997-05-01), Ausschnitt
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patent: 5757507 (1998-05-01), Auschnitt et al.
patent: 5790254 (1998-12-01), Ausschnitt
IBM Technical Disclosure Bulletin, vol. 32, No. 12, p240, May 1990.

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