Method and test circuit for testing memory internal write...

Details Method and test circuit for testing memory internal write... Method and test circuit for testing memory internal write...

2006-11-21

2006-11-21

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000, C365S201000

Reexamination Certificate

active

07139946

ABSTRACT:
A method of testing write enable lines of random access memory having at least one word having one or more write enable inputs for controlling write operations in the word, comprises, for a selected memory address, shifting a series of test bits through an addressed word via a first data input to the word, and for each test bit, performing a write operation to the word using a write enable test input derived from data outputs of the word or from a test write enable signal applied concurrently to each write enable input; and, after each write operation, comparing a last bit of the word against an expected value to determine whether there exists a defect in a write enable line.

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SISO (Wayback Machine Archive: http://ourworld.compuserve.com/homepages/g—knott/elect339.htm, Published on Feb. 17, 2001).

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