Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2007-10-23
2007-10-23
Lamarre, Guy (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C398S140000
Reexamination Certificate
active
09841799
ABSTRACT:
A circuit using modular based parallel processing calculates the cumulative parity of a binary number input sequence. The circuit is used, for example, to implement a precoder for an optical duobinary transmission system. The design permits a relatively low-speed circuit to be used as the precoder before a time-division multiplexer. The parallel circuit can be scalable to process a very large number of sets of parallel binary data by the usage of two basic modules, namely, a parity module and a delay module.
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Ho Ricky Keang-Po
Kahn Joseph M.
Lamarre Guy
Pillsbury Winthrop Shaw & Pittman LLP
Rizk Sam
Stratalight Communications, Inc.
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