Method and system to access memory

Details Method and system to access memory Method and system to access memory

2011-04-19

2011-04-19

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S233100, C365S236000, C365S210100

Reexamination Certificate

active

07929356

ABSTRACT:
This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.

REFERENCES:
patent: 5440515 (1995-08-01), Chang et al.
patent: 6185128 (2001-02-01), Chen et al.
patent: 6891774 (2005-05-01), Abdollahi-Alibeik et al.
patent: 7646658 (2010-01-01), Chen et al.

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