Method and system of providing a cache-coherency protocol for ma

Details Method and system of providing a cache-coherency protocol for ma Method and system of providing a cache-coherency protocol for ma

1997-04-14

1999-08-24

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711141, 711145, G06F 1200

Patent

active

059436840

ABSTRACT:
A method and system of providing a cache-coherency protocol for maintaining cache coherency within a multi-processor data-processing system is disclosed. In accordance with the method and system of the present invention, each processor has a cache hierarchy of at least a first-level cache and a second-level cache, and the first-level cache is upstream of the second-level cache. Each of the caches includes multiple cache lines, each associated to a state-bit field utilized for identifying at least six different states of the cache lines, including a Modified state, an Exclusive state, a Shared state, an Invalid state, a Recently-Read state, and an Upstream-Undefined state. In response to an indication of a cache line containing a copy of information that was most recently accessed, the state of the cache line is transitioned from the Invalid state to the Recently-Read state. In response to an information modification of a cache line in the first-level cache without performing a linefill operation, the state of the cache line is transitioned from the Invalid state to the Upstream-Undefined state.

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