Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-06-06
2006-06-06
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S134000, C711S133000, C711S118000, C711S122000
Reexamination Certificate
active
07058766
ABSTRACT:
A method for adaptively managing pages in a cache memory with a variable workload comprises defining a cache memory; organizing the cache into disjoint lists of pages, wherein the lists comprise lists T1, T2, B1, and B2; maintaining a bit that is set to either “S” or “L” for every page in the cache, which indicates whether the bit has short-term utility or long-term utility; ensuring that each member page of T1is marked either as “S” or “L”, wherein each member page of T1and B1is marked as “S” and each member page of T2and B2is marked as “L”; and maintaining a temporal locality window parameter such that pages that are re-requested within a window are of short-term utility and pages that are re-requested outside the window are of long-term utility, wherein the cache comprises pages that are members of any of lists T1and T2.
REFERENCES:
patent: 4463424 (1984-07-01), Mattson et al.
patent: 4802086 (1989-01-01), Gay et al.
patent: 5649156 (1997-07-01), Vishlitzky et al.
patent: 6078995 (2000-06-01), Bewick et al.
patent: 6378043 (2002-04-01), Girkar et al.
patent: 6631446 (2003-10-01), Cherkauer et al.
patent: 6738866 (2004-05-01), Ting
patent: 6745295 (2004-06-01), Rodriguez
patent: 6748491 (2004-06-01), Rodriguez
patent: 6775745 (2004-08-01), Fry et al.
patent: 2003/0105926 (2003-06-01), Rodriguez
patent: 2004/0098541 (2004-05-01), Megiddo et al.
Improving Disk Cache Hit-Ratios Through Cache Partitioning, Dominique et al. IEEE Log No. 9105059. Jan. 12, 1990.
LRU-SP: A size-Adjusted and Popularity-Aware LRU Replacement Algorithm for Web Caching, Kai et al. Graduate school of Informatics, Kyoto University. 0-7695-0792-1/00 copy right 2000 IEEE.
Reducing Cache Conflicts by Multi-level Cache Partitioning and Array Elements Mapping. Chih-Yung Chang, Dept. of Computer and Information Science, Aletheia University, 0-7695-0566-6/00 IEEE.
LRFU: A Spectrum of Policies that Subsumes the Least Recently Used and Least Frequently Used Policies, Donghee Lee et al. Mar. 10, 2000. IEEECS Log No. 111694.
ARC: A Self-Tuning,Low Overhead Replacement Cache, Megiddo et al. USENIX File & Storage Technologies Conference (FAST), Mar. 31, 2003.
Gibb I.P. Law Firm LLC
International Business Machines - Corporation
McCabe, Esq. Mark C.
Padmanabhan Mano
Patel Kaushikkumar
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