Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-04-01
2002-04-23
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S733000, C714S735000, C714S736000
Reexamination Certificate
active
06378094
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to testing electronic printed circuit or wiring boards and, more particularly, to a system and method for testing digital clusters on a circuit board in a boundary scan environment.
2. Description of the Related Art
The testing of individual circuit boards in a system made up of one or more circuit boards is becoming more and more difficult due at least in part to the shrinking of the area between the components on the boards, and to the increasing complexity of the components and the interconnections between them on the board. The reduction in size of components allows more components to fit onto each board, and thereby enables additional processing of information in less physical space than previously required.
With this shrinking technology, manual testing using an automatically controlled probe is becoming more difficult. In some cases, the probe is not small enough to physically contact the interconnections between the miniaturized circuit components. In an effort to implement testing of these components, newer components with built in testing circuitry are being designed. These components are generally referred to as boundary scan components.
Boundary scan circuit components are designed to include additional circuitry to aid in the testing of the component and its interconnection with other components. The boundary scan circuitry typically includes a test data in (TDI) pin and a test data out (TDO) pin having corresponding registers associated with each. In addition, controller circuitry added to each boundary scan circuit component includes a test access port (TAP) that enables the boundary scan testing of the respective element. IEEE standard 1149.1 governs the design, registers, protocols and testing of boundary scan elements.
A group of boundary scan elements are serially connected to each other via their respective TDI and TDO pins. For example, if chip A and chip B are the boundary scan components to be tested, the TDO pin of chip A is connected to the TDI pin of chip B. During testing, a serial test vector can be applied to the TDI pin of chip A and the output at the TDO pin of chip B monitored to determine whether the two chips are operating according to a predetermined design.
Unfortunately, circuit boards in present systems are not formed in their entirety of boundary scan components. That is, circuit boards typically consist of a combination of boundary scan components and non boundary scan elements; the latter are commonly referred to as cluster components. A circuit board may have one or more groups of cluster components which are often referred to as clusters. The combination of boundary scan and cluster components presents a problem in testing the circuit board at the component level.
One known approach to testing circuit boards having both boundary scan and non boundary scan elements is referred to as functional testing. Functional testing applies functional vectors to the input of the circuit, and then evaluates the circuit function resulting from the application of these test vectors. Since exhaustive functional testing is very expensive to implement, generally incomplete functional testing is performed to provide cost efficient manufacturing. This incomplete functional testing results in a very low quality structural test and does not provide sufficient detail about which components are not operating properly, or which interconnection between components is faulty. Thus, functional testing does not enable testing of the individual cluster circuit components and the interconnections between them and with the boundary scan components. In the event that a circuit fails the functional test, no diagnosis can readily be performed to identify the faulty component or interconnection.
The functional test vectors are provided to the system by the designers, and cannot be generated automatically. Furthermore, since functional testing does not require the identification of cluster components, a faulty component or interconnection between cluster components cannot be diagnosed for repair.
SUMMARY OF THE INVENTION
The present invention overcomes the shortfalls of functional testing used for structural testing by providing a system and method for testing circuit clusters in a boundary scan environment that enables the diagnosis of individual cluster circuit components and interconnections.
In accordance with an embodiment of the present invention, the method comprises the steps of identifying clusters and boundary scan elements that make up a circuit; creating a gate level cluster netlist for each identified cluster; generating test vectors for all possible faults in the clusters; serializing the test vectors for application using standard boundary scan testing; applying the serialized test vectors to an input of the cluster via a first boundary scan IC connected thereto; and observing the response as a corresponding boundary scan chain produced at a second boundary scan IC.
The identification of clusters and boundary scan elements categorizes the clusters with respect to neighboring boundary scan elements (ICs), and provides an indication as to which boundary scan elements can be used to test the identified clusters. This permits the TDI and TDO pins of the respective input and output boundary scan elements to be used in testing the corresponding cluster, in addition to the TAP and controller information of the corresponding boundary scan elements.
The generation of the gate level cluster netlist substantially merges all of the gate level information for all chips within each identified cluster to create an integrated netlist of each cluster. The generated netlist includes information relating to the interconnection of the circuit elements within each identified cluster.
In accordance with a preferred embodiment of the invention, the test vectors are generated such that stuck-at faults, stuck-open faults, pairwise shorts, and the interconnections between cluster circuit elements can be tested. The test vectors are generated in parallel and subsequently serialized for input into the cluster under test as a boundary scan chain at the TDI of one boundary scan element.
The resulting output from the TDO pin of the corresponding boundary scan element provides the test results. The test results are logged and enable the test technician to diagnose any faults occurring in the cluster for subsequent repair or redesign.
According to a preferred embodiment, during the generation of the parallel test vectors, a fault list or report is created identifying each generated test vector and the particular fault that it is has been generated to detect. Therefore upon receiving the output of the test in the form of a boundary scan chain, the logged test results can be used in conjunction with the created fault list/report to aide in the diagnosis of the cluster circuit components and interconnections between them.
Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
REFERENCES:
patent: 5260946 (1993-11-01), Nunally
patent: 5444716 (1995-08-01), Jarwala et al.
patent: 5513188 (1996-04-01), Parker et al.
patent: 5570375 (1996-10-01), Tsai et al.
Chakraborty Tapan Jyoti
Van Treuren Bradford Gene
Lucent Technologies - Inc.
Moise Emmanuel L.
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