Method and system for testing chips

Details Method and system for testing chips Method and system for testing chips

2007-01-29

2010-12-14

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S712000

Reexamination Certificate

active

07853843

ABSTRACT:
Method and related system for testing a chip with high speed I/O functions are provided. The testing method of a chip includes the steps of: receiving a testing signal from a low speed bus; then transmitting the testing signal according to a transmission control signal; then receiving the testing signal according to a receiving control signal; and comparing the transmitted testing signal and the received testing signal to identify the I/O functions of the chip.

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patent: 2002/0030531 (2002-03-01), Jaynes
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patent: 564309 (2003-12-01), None
patent: 200624843 (2006-07-01), None

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