Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-11
2002-08-20
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
06438722
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to an improved method and system for testing an integrated circuit and more particularly to a test chip for testing a complex integrated circuit. Still more particularly, the present invention relates to a method and system for detecting errors in a subset of the complex integrated circuit which is embedded within a test chip, independent of the complex integrated circuit.
2. Description of the Related Art
As integrated circuit technology has advanced, the a complexity and density of circuit devices formed within a single chip has increased dramatically. Consequently, several problems have arisen with regard to testing proper operation of such integrated circuits. For example, while the methodology for testing an integrated circuit (IC) may be relatively straight forward, most IC chips typically have far fewer I/O pins available to a circuit tester than are required to adequately test the IC and at the same time maintain the cost and functionality thereof. In addition, most high end commercial testers can not provide a large number of I/Os at speed to adequately test the design.
A general solution to the above-described problem is to embed a majority of the test circuitry on the chip itself rather relying solely on an external testing mechanism. Such testing facilities are frequently referred to as built-in self-test(BIST), array self-test(AST), array built-in self-test (ABIST), or logical built-in self-test(LBIST) circuits and will hereinafter be referred to generically as BIST circuits. BIST circuits are typically controlled by an external tester which provides a clock signal, scans test data in and scans results out of the BIST circuit. In general, a BIST circuit applies the received test data to functional units within an integrated circuit in which the BIST circuit is embedded and then compares the data output therefrom with expected data. In addition the data output from the functional units during testing is scanned out to a memory array within the external tester. In response to a discrepancy between the output data and the expected data, the BIST circuit indicates that a failure has been detected and after a delay, the application of data is halted and eventually the cycle during which the failure occurred is detected from data which is scanned out. Thereafter, the BIST circuit is re-run to the cycle in which the failure occurred. The state machine data at the failing cycle is then scanned out and utilized to generate a bit-fail map for use in failure analysis.
A general shortcoming of the BIST testing methodology is the inability of the cycle of failure to be precisely detected at typical operating speeds of fast memories (e.g. greater than 200 MHz) because of the latency of data transmittal between the BIST circuit and the external tester. In order to properly detect the cycle of failure after the BIST is halted, complex algorithms are typically employed which may take many hours or even days to determine the cycle of failure. Further complicating this shortcoming is the increase in the volume of data which is processed in a period of time as IC speeds increase (e.g. greater than 1 GHz). In testing complex integrated circuits, and in particular in testing processors, it is desirable to determine faults as quickly as possible in order to decrease time to develop faster processor speeds.
Further, no commercial external tester is available which can provide data patterns to a BIST circuit of an AIC at speed for frequency ranges such as 1 GHz or greater and with a large number of channels (i.e. greater than 640 channels). Thereby, even though the operational frequency of the chip may be 1 GHz, during testing, the frequency of operation would be limited by the latency of transfer between the external tester and the IC. In addition, specialized I/O circuits which could communicate with the external tester to send and receive signals at this high rate of frequency would be necessary in an IC, adding circuit complexity to the IC for testing purposes. Further limiting the testing of an IC, a BIST circuit cannot test data over continuous functional clock cycles because a pattern must be scanned in, a few functional clock cycles issued, and a result scanned out.
Importantly, in adding BIST circuitry to an IC, the complexity of BIST testing circuitry must be balanced with the functional circuitry of the IC. However, in designing for increased processor speeds, such as 1 GHz or greater, the volume of processor operations which can be performed per cycle is increased, thereby increasing the complexity of circuitry and the number of data paths within the functional units of the IC which need to be checked for errors. Thereby, the width of test data vectors needed to properly test the functionality of such a processor is expanded to such a point that testing the processor with a BIST test would add an undesirable amount of circuitry. In addition, supplying a wider test vector from the external tester to the IC would further add to the latency of transmittal between external tester and IC.
In addition, BIST circuits do not have the advantage of providing test data subject to environmental conditions present within an integrated circuit such as noise, temperature, frequency limitations, etc. In particular, when designing for increased processor speeds such as 1 GHz or greater, these environmental conditions are expected to be magnified in comparison to slower processor speeds.
Therefore, as production technologies are improving to provide for the manufacture of ICs which operate at very high frequencies, testing technology utilized to test these faster chip is needed. As should thus be apparent, an improved method for testing a complex integrated circuit is needed such that a cycle of failure may be detected in a timely manner, the width of test data vectors may be expanded in order to properly test the functionality of the complex integrated circuit, test data vectors may be provided and the results detected at speed, and conditions of operation such as environmental conditions and operation over a range of frequencies may be tested.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved method and system for testing an integrated circuit.
It is another object of the present invention to provide a test chip for testing an integrated circuit.
It is yet object of the present invention to provide a method and system for detecting errors in an integrated circuit by subsets which are embedded within a test chip, independently of testing the integrated circuit in its entirety.
The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit designed for manufacture by a particular production technology are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by subsets, independently of testing the entire integrated circuit.
It is an advantage of the method and system that the design process of the complex integrated circuit proceeds with efficiency by correcting errors found in the subset thereof.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5170398 (1992-12-01), Fujueda et al.
Bailey Roger Ned
Floyd Michael Stephen
McCredie Bradley
Reick Kevin Franklin
Stigdon Hugh Rodney
Bracewell & Patterson L.L.P.
Chung Phung M.
England Anthony V. S.
International Business Machines - Corporation
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