Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-12-28
2002-07-23
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06425104
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a system for generating a test pattern used for fault detection or the like of a large scale integrated circuit (LSI) as well as a computer readable medium instructing the system to perform the method. More particularly, the invention relates to a method and a system suitable for the case where the entirety of an objective circuit for test pattern generation is divided into a plurality of subcircuits and a test pattern generating method and a system suited for generating test patterns for these subcircuits by means of distributed processing, as well as a computer readable medium instructing the system to perform the method.
2. Description of Related Art
Accompanying the increase in complexity and enlargement in scale of the integrated circuits such as LSIs, techniques are in fashion in which the entirety of an objective circuit for test pattern generation is divided into a plurality of subcircuits with a specified scale, and the test pattern generation for each subcircuit is processed distributedly by means of a plurality of computers. The inventor of the present invention and others disclosed such a method as Japanese Laid Open Patent Publication No. 11-211801 and No. 11-237450, which were laid open after the priority date of the present invention. Their invention has been filed in US patent application as Ser. No. 09/236,903.
FIG. 11
shows a schematic configuration of such a test pattern generation system employing a circuit division distributed processing technique. As shown, in this test pattern generation system a plurality of engineering work stations (EWSs) are interconnected via a network NW such as a local area network (LAN). Note, however, that beside the mode shown in the figure, various kinds of other mode, such as one in which a plurality of central processing units (CPUs) are connected by busses to a single computer with multiprocessor configuration, are also conceivable.
In the figure, each of EWSs
1
-
1
to 1—n (n is a natural number) is a computer in charge of automatic generation processing of a test pattern, and performs at one point in time, test pattern generation for one subcircuit. In what follows, the CPU mounted on each EWS will be referred to as “remote CPU”. In general, the total number of subcircuits obtainable by circuit division is set to be a number far greater than the number n of the remote CPUs. On the other hand, EWS
1
-
0
is a computer which integrally controls the EWSs
1
-
1
to 1−n, and after division of the entirety of the object of test pattern generation into subcircuits, performs distributed processing of test pattern generation for the entire circuit by letting EWSs
1
-
1
to 1−n execute test pattern generation processing for respective subcircuits. In the following, the CPU mounted on the EWS
1
-
0
will be referred to as “local CPU”.
The local CPU hands over information (“subcircuit information” in the figure showing the constitution of the subcircuits and a collection of fault information (“fault list” in the figure) to be detected for respective subcircuits to each remote CPU, and requests them to generate test patterns for the subcircuits. The fault information includes fault position information for the entire circuit, identification information showing whether the fault is a “1” fault or a “0” fault, and the like. In the meantime, a remote CPU requested the processing by the local CPU generates a test pattern based on the received subcircuit information and fault list and sends the result back to the local CPU. In addition, it determines information on the faults which were undetectable by the generated test pattern and reports it back to the local CPU. Here, the local CPU is constantly watching the processing conditions to see whether respective remote CPUs are in the process of executing test pattern generation. Whenever the result of test pattern generation (pattern and undetected fault information) is reported back from some remote CPU, the local CPU retrieves remote CPUs in idle state which are not executing the test pattern generation processing, selects a subcircuit which has not yet completed the processing, and requests an idle remote CPU to generate a test pattern for that subcircuit.
Now, the size (here, the number of gates) of the subcircuit obtained by the circuit subdivision is calculated in advance to be a prescribed value based on the evaluation in consideration of obtaining the optimum processing efficiency of test pattern generation. Accordingly, the local CPU performs circuit subdivision so as to have the size of the subcircuit to be approximately equal to the prescribed value. In this case, a subcircuit is constructed by collecting a plurality of circuit blocks called “cones” which will be described later. In
FIG. 12
which illustrates a circuit diagram for only a part extracted from the entire circuit which is the object of test pattern generation, symbols Ti
1
to Ti
7
are input terminals, symbols To
1
and To
2
are output terminals, and symbols
5
-
1
to
5
-
6
are logic gates. In addition, symbols
6
-
1
and
6
-
2
are circuit block composed of the input terminals, output terminal, and logic gates, which will be called cones in this invention, so named in association with the shapes of the cross section of cones along the axes. Moreover, since these input terminals and the output terminal act as the interfaces between the circuit as a whole and the outside, these are sometimes called external input terminals and an external output terminal.
The cones are in 1 to 1 correspondence with the output terminals, and a cone is defined as a set of all the logic gates passed through and all the input terminals arrived at, and the output terminal being the starting point, before one arrives at input terminals when one traces logic gates sequentially starting from an output terminal toward the input terminals. In other words, a cone is formed by the collection of all the logic gates and input terminals through which a logical value can be propagated to a certain output terminal, together with that output terminal. For example, when the paths within the circuit are traced with the output terminal To
1
as a starting point, since the output terminal To
1
is connected to the logic gate
5
-
1
, the logic gate is included in the cone
6
-
1
. Further, the logic gate
5
-
1
is connected to the input terminals Ti
1
and Ti
2
and the logic gate
5
-
2
. Since, however, the logic gate
5
-
2
is not connected in the direction from the output terminal To
1
to the input terminal, it is excluded and only the input terminals Ti
1
and Ti
2
are included in the cone
6
-
1
. That is, the cone
6
-
1
is composed of the output terminal To
1
, the logic gate
5
-
1
, and the input terminals Ti
1
and Ti
2
. The cone
6
-
2
is formed by the same procedure, and it includes the output terminal To
2
, the logic gates
5
-
2
to
5
-
6
, and the input terminals Ti
2
to Ti
7
. As is clear from the above description, the entirety of the circuit which is the object of the test pattern generation includes cones equal to the number of its output terminals.
Although not shown in
FIG. 12
, in a scannable object circuit for test pattern generation, scannable flip-flops (abbreviated as FFs hereinafter) included in the circuit are handled as objects completely equivalent to the input or output terminals. In other words, those components to which logical values can be set or referred to from the outside of the circuit are handleable as being completely equivalent to the input or output terminals. Accordingly, if a scanning FF is arrived at when tracing a circuit in the direction from an output terminal toward the input terminal, the scanning FF can be regarded as equivalent to an input terminal as well as an output terminal, so that a new cone can be defined with the scanning FF as a starting point. Incidentally, in order to avoid complication, only circuits which do not include scanning FFs will be described in t
Chase Shelly A
De'cady Albert
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