Method and system for temperature compensation for memory...

Details Method and system for temperature compensation for memory... Method and system for temperature compensation for memory...

2006-06-06

2006-06-06

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189070, C365S207000

Reexamination Certificate

active

07057958

ABSTRACT:
The preferred embodiments described herein relate to a method and system for temperature compensation for memory cells with temperature-dependent behavior. In one preferred embodiment, at least one of a first temperature-dependent reference voltage comprising a negative temperature coefficient and a second temperature-dependent reference voltage comprising a positive temperature coefficient is generated. One of a wordline voltage and a bitline voltage is generated from one of the at least one of the first and second temperature-dependent reference voltages. The other of the wordline and bitline voltages is generated, and the wordline and bitline voltages are applied across a memory cell. Other methods and systems are disclosed for sensing a memory cell comprising temperature-dependent behavior, and each of the preferred embodiments can be used alone or in combination with one another.

REFERENCES:
patent: 3851316 (1974-11-01), Kodama
patent: 4592027 (1986-05-01), Masaki
patent: 4646266 (1987-02-01), Ovshinsky et al.
patent: 4646269 (1987-02-01), Wong et al.
patent: 4698788 (1987-10-01), Flannagan et al.
patent: 4744061 (1988-05-01), Takemae et al.
patent: 4873669 (1989-10-01), Furutani et al.
patent: 5107139 (1992-04-01), Houston et al.
patent: 5149199 (1992-09-01), Kinoshita et al.
patent: 5276644 (1994-01-01), Pascucci et al.
patent: 5276649 (1994-01-01), Hoshita et al.
patent: 5278796 (1994-01-01), Tillinghast et al.
patent: 5359571 (1994-10-01), Yu
patent: 5383157 (1995-01-01), Phelan
patent: 5410512 (1995-04-01), Takase et al.
patent: 5652722 (1997-07-01), Whitefield
patent: 5784328 (1998-07-01), Irrinki et al.
patent: 5818748 (1998-10-01), Bertin et al.
patent: 5835396 (1998-11-01), Zhang
patent: 5890100 (1999-03-01), Crayford
patent: 5923588 (1999-07-01), Iwahashi
patent: 5925996 (1999-07-01), Murray
patent: 5940340 (1999-08-01), Ware et al.
patent: 5961215 (1999-10-01), Lee et al.
patent: 5977746 (1999-11-01), Hershberger et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6034918 (2000-03-01), Farmwald et al.
patent: 6055180 (2000-04-01), Gudesen et al.
patent: 6070222 (2000-05-01), Farmwald et al.
patent: 6157244 (2000-12-01), Lee et al.
patent: 6185121 (2001-02-01), O'Neill
patent: 6185712 (2001-02-01), Kirihata et al.
patent: 6205074 (2001-03-01), Van Buskirk et al.
patent: 6208545 (2001-03-01), Leedy
patent: 6212121 (2001-04-01), Ryu et al.
patent: 6236587 (2001-05-01), Gudesen et al.
patent: 6240046 (2001-05-01), Proebsting
patent: 6246610 (2001-06-01), Han et al.
patent: 6335889 (2002-01-01), Onodera
patent: 6356485 (2002-03-01), Proebsting
patent: 6373768 (2002-04-01), Woo et al.
patent: 6385074 (2002-05-01), Johnson et al.
patent: 6407953 (2002-06-01), Cleeves
patent: 6420215 (2002-07-01), Knall et al.
patent: 6424581 (2002-07-01), Bosch et al.
patent: 6507238 (2003-01-01), Yang
patent: 6525953 (2003-02-01), Johnson
patent: 6560152 (2003-05-01), Cernea
patent: 6577549 (2003-06-01), Tran et al.
patent: 6697283 (2004-02-01), Marotta et al.
patent: 6724665 (2004-04-01), Scheuerlein et al.
patent: 6754124 (2004-06-01), Seyyedy et al.
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2002/0136045 (2002-09-01), Scheuerlein
patent: 2002/0136047 (2002-09-01), Scheuerlein
patent: 2003/0043643 (2003-03-01), Scheuerlein et al.
patent: 2003/0046020 (2003-03-01), Scheuerlein
“A 14ns 1Mb CMOS SRAM with Variable Bit-Organization,” Wada et al., 1988 IEEE International Solid-State Circuits Conference, pp. 252-253 (Feb. 19, 1988).
“Partial Selection of Passive Element Memory Cell Sub-Arrays for Write Operation,” U.S. Appl. No. 09/748,649, filed Dec. 22, 2000; inventors: Roy E. Scheuerlein and Matthew P. Crowley.
“64M x 8 Bit NAND Flash Memory,” Samsung Electronics (Oct. 27, 2000).
“How Flash Memory Works,” wysiwyg://8/http://www.howstuffworks.com/flash-memory.htm?printable=1, 5 pages (1998).
“Datalight FlashFX™ 4.06 User's Guide,” p. 11 (Aug. 2000).
“How Does TrueFFS® manage Wear Leveling?,” http://www.m-sys.com/content/information/calcInfo.asp, 2 pages (printed Oct. 5, 2001).
“A CMOS Bandgap Reference Circuit with Sub-1V Operation,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999, pp. 670-674.
“Sub-1V CMOS Proportional to Absolute Temperature References,” IEEE Journal of Solid-State Circuits, vol. 38, No. 1, Jan. 2003, pp. 85-89.
“The flash memory read path: building blocks and critical aspects,” Micheloni et al., Proceedings of the IEEE, vol. 91, No. 4, Apr. 2003, pp. 537-553.
“A current-based reference-generations scheme for 1T-1C ferroelectric random-access memories,” Siu et al., IEEE Journal of Solid-State Circuits, vol. 38, Issue 3, Mar. 2003, pp. 541-549.

Affiliated with

Also associated with

Rating

Method and system for temperature compensation for memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for temperature compensation for memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for temperature compensation for memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3616783