Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-08-30
2004-12-07
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06829737
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit test circuits and methods. In particular, the present invention relates to storage of test result data on an integrated circuit device in nonvolatile memory elements and, most particularly, to the inclusion of logic in the integrated circuit device for determining the results of device tests and enabling the storage of test results in the nonvolatile memory elements.
2. Statement of the Art
Semiconductor integrated circuit devices are manufactured on wafers or other substrates of semiconductor material. Conventionally, many devices are manufactured on a single wafer and individual devices or groups of devices are cut from the wafer and packaged. The devices are tested at various points during the manufacturing process, e.g., with electrical probes while they are still on the wafer, in die form (after singulation but prior to packaging) and after packaging.
During testing, a particular signal or combination of signals is input to the device and the output value or values read from the device are compared with values expected to be obtained from a properly functioning device. Tests may involve a particular signal or combination of signals being delivered repetitively, perhaps under extreme environmental conditions (temperature, voltage, etc.) in order to identify a device which would fail after a shorter than usual period of use (“burn-in” testing). Other tests may involve a number of different signals or signal combinations delivered in sequence. One method for testing a memory device is to deliver the same signal/signal combination to multiple identical subsections of the device simultaneously and compare the values read from the subsections (“compression testing”). If all of the respective, read values match, the test has been passed, while a mismatch between respective values read from any of the subsections indicates a device malfunction and failure of the test.
A particular test or test sequence often includes multiple test steps. Moreover, a complete test flow will often require that devices move from one piece of test equipment to another. For example, a first piece of test equipment and test fixtures may be utilized for probe testing, another for burn-in testing and yet another for packaged device testing after burn-in.
After a particular test or test sequence has been completed, devices which have failed some or all of a test may be separated from the good devices. However, a device which has failed one portion of the test sequence may pass subsequent test sequences, so if it is erroneously placed into the “good” bin and then passes subsequent tests it may eventually be classified and sold as fully functional. One way to avoid this type of error is to store information regarding the test history of the device on the device itself in nonvolatile memory elements. One example describing storage of test results in nonvolatile memory on a semiconductor device is co-pending U.S. patent application Ser. No. 08/946,027, the disclosure of which is hereby incoporated herein by reference.
Test equipment used for testing integrated circuit devices conventionally transmits a test signal and then receives an output signal from the integrated circuit device. The test equipment then compares the output signal from the integrated circuit device with the value expected to be obtained from a properly functioning device and sends an instruction to the device which causes a specific nonvolatile memory element to be set to indicate either pass or fail of the test step. A series of nonvolatile memory elements may be set to indicate the results of a series of test or test steps. The tester thus must include detectors and comparators so that it can read the output signal and perform a comparison to determine passage or failure of the test.
It would be advantageous to decrease the cost and complexity of the tester by eliminating the need for detectors and comparators on the test equipment.
It would be advantageous to eliminate the need for intelligence in device test equipment, by instead placing intelligence on the device being tested.
It would be desirable to provide for the storage of information concerning correct application of test sequences to the device on the device itself.
These and other advantages are provided by the invention.
SUMMARY OF THE INVENTION
The present invention includes a method and system for storing semiconductor device test results on a tested device, using on-device test circuitry for the determination of test results and control of test result storage. The semiconductor device, which may be a memory device, a microprocessor, or other semiconductor device, includes a plurality of nonvolatile memory elements which are set to indicate the results of a series of multiple tests or test steps. The semiconductor device may also include comparator circuitry, which compares test signals sent to the semiconductor device from a tester with data values read from the semiconductor device following receipt of the test signals, or which performs a comparison between data values read from multiple regions of a device, to determine correct functioning of the device. The semiconductor device includes a latch which is set to indicate passage or failure of the test. The latch enables circuitry which causes a nonvolatile memory element to be set upon receipt of an instruction from the tester. The latch, and subsequently the nonvolatile memory element, are set to represent the test results according to a predetermined rule. Typically, one logic level is latched to represent passage of a test and another is used to represent failure of the test. For example, logic high could represent pass and logic low would then represent fail or, alternatively, logic low could represent pass and logic high represent fail. Similarly, the nonvolatile memory element is set to one state to represent passage of a test and another to represent failure of the test.
By locating the circuitry that controls setting of memory elements to represent test results on the device being tested, the tester equipment does not need to receive values from the device being tested, perform a comparison between test values and received values to determine the outcome of the test, or determine whether a memory element should be set to store the test result. The tester needs only to transmit test signals and set signals to the semiconductor device, without receiving any values back from the semiconductor device. Accordingly, the design and construction of the test equipment can be simplified considerably.
In one embodiment of the invention, a rule used to determine the settings of latches and nonvolatile memory elements to represent pass/fail status is dependent on the test or test step being performed. That is, for certain tests/test steps a first state would represent pass and a second state would represent fail, while for other tests/test steps the second state would represent pass and the first state would represent fail. Therefore, a device which had passed all tests would be expected to have nonvolatile memory elements set in a predetermined pattern of first and second states. The pattern of first and second states corresponding to a known good device is obtained only when the device has been properly connected to the test equipment, received appropriate test signals and passed all tests.
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patent:
Chase Shelly A
Micro)n Technology, Inc.
Ton David
TraskBritt
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