Method and system for securing instruction caches using...

Details Method and system for securing instruction caches using... Method and system for securing instruction caches using...

2008-07-31

2011-11-08

Choe, Yong (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S202000, C711SE12017

Reexamination Certificate

active

08055848

ABSTRACT:
A method and system is provided for securing micro-architectural instruction caches (I-caches). Securing an I-cache involves maintaining a different substantially random instruction mapping policy into an I-cache for each of multiple processes, and for each process, performing a substantially random mapping scheme for mapping a process instruction into the I-cache based on the substantially random instruction mapping policy for said process. Securing the I-cache may further involve dynamically partitioning the I-cache into multiple logical partitions, and sharing access to the I-cache by an I-cache mapping policy that provides access to each I-cache partition by only one logical processor.

REFERENCES:
patent: 7788650 (2010-08-01), Johnson et al.
patent: 2008/0229052 (2008-09-01), Ozer et al.

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