Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-02-17
2009-06-02
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C714S742000, C365S201000
Reexamination Certificate
active
07543200
ABSTRACT:
An efficient and low-cost method for testing multiple DUTs in a parallel test system is disclosed. In one embodiment, a method for scheduling tests in a parallel test system having at least two devices-under-test (DUTs) coupled to a test controller through one or more vendor hardware modules includes receiving a test plan comprising a plurality of tests arranged in a predetermined test flow, where the predetermined test flow comprises a plurality of tests arranged in a directed graph and each test is arranged as a vertex in the directed graph, determining a test execution schedule in accordance with the test plan at runtime, where the test execution schedule identifies a set of next tests to be executed according to current states of the at least two DUTs and where the set of next tests include different tests to be performed on different DUTs, and testing the at least two DUTs using the test execution schedule.
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Adachi Toshiaki
Elston Mark
Pramanick Ankan
Advantest Corporation
Britt Cynthia
Merant Guerrier
Morrison & Foerster / LLP
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