Method and system for scaling nonvolatile memory cells

Details Method and system for scaling nonvolatile memory cells Method and system for scaling nonvolatile memory cells

2002-05-15

2004-10-19

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S306000, C438S307000, C257S316000, C257S408000

Reexamination Certificate

active

06806155

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to a method and system for providing a nonvolatile memory cell that is scalable.
BACKGROUND OF THE INVENTION
Nonvolatile memory devices are used for a variety of applications. Such conventional semiconductor devices typically include gate stacks which are part of devices, such as memory cells. Generally, a source is positioned at one edge of the gate stack, while the drain is at the opposing end of the gate stack. Field insulating regions generally run perpendicular to the gate stacks and are typically used to electrically isolate different devices. The field insulating regions are typically composed of oxide. In addition, electrical connection is made to the sources.
In order to fabricate a conventional nonvolatile memory device, gate stacks are formed and oxidized. A mask which exposes only the regions in which the sources will be formed is provided. A conventional source side implant of boron (B+) is provided. The mask is removed and mask which only exposes the drain side is provided. A conventional drain side implant, typically of arsenic, is then provided and annealed. A self-aligned source etch mask and etch is then provided. The self-aligned source edge masks the drain side. However, the mask does not extend to the edges of the gate stack at the source side. Thus, the self-aligned source etch is aligned using the gate stacks. The self-aligned source etch removes a portion of the field insulating regions between the sources as well as the oxide layer above the sources. A conventional implant which connects the sources is then provided. The conventional implant is typically a high dose As implant, on the order of 3×10
15
ions/cm
2
. Spacers are then formed at the edges of the gate stack, and CoSi formed on the drain and tops of the gate stack. Thus, contact can also be made to the drains and gate stacks.
Although the conventional nonvolatile memory cell functions, one of ordinary skill in the art will readily realize that that fabrication of the conventional nonvolatile memory cell requires a number of masks for which alignment is critical. In particular, the masks for the boron implant, the drain side implant and the source connection implant must be properly aligned to ensure that the correct portion of the conventional semiconductor device is implanted. This alignment becomes increasingly difficult as the size of the memory cell decreases. As a result, fabrication of a smaller memory cell would be more difficult.
Accordingly, what is needed is a system and method for providing a semiconductor device that can more readily be scaled down in size. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for providing a semiconductor device. The method and system comprise providing a plurality of gate stacks and a first source and drain halo implant. The first source and drain halo implant uses the plurality of gate stacks as a mask. The method and system also comprise providing a lightly doped source and drain implant and a N+ source and drain implant. The source connection implant is for connecting a portion of the plurality of sources. The second source and drain implant uses the plurality of gate stacks as a mask.
According to the system and method disclosed herein, the present invention source and drain implants, each of which uses the gate stacks as a mask are used, thereby reducing the number of alignment-critical masks used during fabrication.


REFERENCES:
patent: 5395773 (1995-03-01), Ravindhran et al.
patent: 6448141 (2002-09-01), Ahmad et al.
patent: 2002/0153559 (2002-10-01), Yeap et al.

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