Method and system for reducing power consumption of a non-blocki

Details Method and system for reducing power consumption of a non-blocki Method and system for reducing power consumption of a non-blocki

1997-09-02

1999-10-26

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711168, 711167, 711163, 711145, 711128, G06F 1316

Patent

active

059745053

ABSTRACT:
A method and system for reducing power consumption of a non-blocking cache memory within a data processing system is disclosed. In accordance with a method and system of the present disclosure, a detection unit, having several index-matching bits, is associated with the cache memory within the data processing system. A determination is made as to whether or not there is a match in the cache memory, in response to an occurrence of a cache request while the cache memory is performing a linefill operation. In response to a determination that there is not a match for the cache request in the cache memory, another determination is made as to whether or not there is a match for the cache request with a block of information within the ongoing linefill operation. In response to a determination that there is a match for the cache request with a block of information within the ongoing linefill operation, one of the index-matching bits is set and clocks to the cache memory are turned off temporarily in order to reduce power consumption by the cache memory.

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Power PC 604 RISC Microprocessor User's manual, "Cache and Bus Interface Unit Operation," Chapter 3, pp. 1-18.
Sonya Gary et al., "PowerPC 603, A Microprocessor for Portable Computers," IEEE Design and Test of Computers, 1994, pp. 14-23.

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