Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-22
2004-04-27
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S399000, C438S586000, C438S597000, C438S638000
Reexamination Certificate
active
06727143
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, such as flash memory devices, more particularly to a method and system for removal of the antireflective-coating layer.
BACKGROUND OF THE INVENTION
A conventional semiconductor device, such as a conventional embedded flash memory, includes several layers of components. For example, memory cells in a memory region of the semiconductor device may be in the layer of components on and just above the substrate. Components in subsequent layers should be electrically insulated from components in layers above and below except where electrical connection is specifically desired to be made. The layer that isolates distinct layers is known as the inter-layer dielectric (“ILD”). Electrical connection to lower layers is made using conventional contacts which extend through the ILD. The conventional contacts typically include via plugs which is extend through via holes in the ILD.
FIG. 1
is a flow chart depicting a conventional method
10
for fabricating a portion of a conventional semiconductor device, such as a conventional embedded flash memory. Components in lower layer are fabricated, via step
12
. For the first ILD, the lower layer is the layer just above the substrate. Thus, step
12
could include fabricating the memory cells in the first layer of the semiconductor device. The ILD is then provided on the lower layer to insulate the lower layer from subsequent, via step
14
. Typically, step
14
includes providing a layer of borophospho-tetraethylorthosilicate (“BPTEOS”) or a layer of borophospho-silicate glass (“BPSG”). Thus, the ILD is typically B or P doped TEOS or a B or P doped silicate glass.
Typically, contact is made to various portions of the lower layer through the ILD. Thus, conventional contacts are fabricated. In order to fabricate a conventional contact, a conventional SiON antireflective coating (“ARC”) layer of a desired thickness is deposited, via step
16
. The desired thickness is typically approximately two hundred to four hundred Angstroms. The ARC layer helps to reduce reflections from the ILD layer and other underlying layers when providing a photoresist structure, as discussed below. The ARC so layer is used because reflections from underlying layers can cause errors in the photoresist structure provided. In particular, without the ARC layer of the desired thickness, the critical dimension of structures formed using the photoresist structure may vary widely from the desired dimension.
A first photoresist structure is then provided on the conventional ARC layer, via step
18
. The first photoresist structure is typically provided by spinning a layer of photoresist onto the ARC layer and using photolithography to develop a pattern, or mask, in the photoresist layer. The photoresist structure includes apertures of the desired size over regions of the ILD in which via holes are desired to be etched.
Once the first photoresist structure has been provided, the conventional via holes are etched in the ILD, via step
20
. The resist structure is then stripped, typically using a dry oxygen ashing and wet etch, via step
22
. Also in step
22
, residues are cleaned. The conventional via holes are filled with a conductive material, forming a conventional via plug, or conventional contact, via step
24
. The conventional via plug is typically composed of W. Thus, electrical contact can be made to structures in the lower layer. However, excess W outside of the conventional via holes should be removed to provide discrete contacts. Furthermore, in order to allow cells in the semiconductor device to be erased using ultraviolet (“UV”) light, the ARC layer may need to be removed. Thus, the excess W is polished away and the ARC layer is removed using a chemical-mechanical polish (“CMP”) step, via step
26
. The ARC layer is polished away at the end of the W polishing step, typically using an oxide buff. Processing of the semiconductor device then continues, via step
28
. Step
28
typically includes fabricating components for subsequent layers and the ILD layers which separate subsequent layers.
FIG. 2A
depicts a portion of a conventional semiconductor device
30
when the first ILD is being formed. In particular,
FIG. 2A
depicts the conventional semiconductor device after step
20
has been performed for the first ILD. The conventional semiconductor device
30
includes memory cells
40
and
50
share a common drain
32
. The ILD
60
and the ARC layer
62
have been deposited. The conventional via holes
64
and
66
have been etched in the ILD
60
. Furthermore, the conventional via holes
64
and
66
have been filled with conventional via plugs to form conventional contacts
68
and
70
.
FIG. 2B
depicts the conventional semiconductor device
30
after step
26
, removal of the ARC layer
62
through CMP has been completed. A second layer of components can be fabricated on the ILD
60
. Because the ARC layer
62
has been removed, the memory cells
40
and
50
can be erased using UV light.
Although the conventional method
10
can be used for fabricating the conventional semiconductor device
30
, one of ordinary skill in the art will readily understand that the conventional method
10
results charge gain and charge loss issues. In particular, components in the semiconductor device
30
may unexpectedly gain or lose charge. For example, charge on the conventional contact
68
may travel to the memory cell
40
or
50
when a user does not desire the memory cell
40
or
50
to store charge. Similarly, a charge stored on the floating gate of the memory cell
40
or
50
may travel to the conventional contact
68
. Thus, a charge intentionally stored on the floating gate
42
may bleed away. The cell
40
or
50
may be subject to unanticipated charge gain and charge loss. As a result, the cell
40
or
50
may not function as desired.
Accordingly, what is needed is a system and method for providing the semiconductor device in which the unexpected charge gain and charge loss are reduced. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device. The method and system comprise providing an interlayer dielectric on the lower layer. The method and system further comprise providing an antireflective coating (ARC) layer. At least a portion of the ARC layer is on the interlayer dielectric. The method and system also comprise providing a plurality of via holes in the interlayer dielectric and the ARC layer and filling the plurality of via holes with a conductive material. The method and system further so comprise removing the ARC layer while reducing subsequent undesirable charge gain and subsequent undesirable charge loss over the use of a chemical mechanical polish in removing the ARC layer.
According to the system and method disclosed herein, the present invention removes the ARC layer without use of a chemical mechanical polish. Consequently, the undesired charge gain and charge loss are reduced.
REFERENCES:
patent: 5786276 (1998-07-01), Brooks et al.
patent: 6222214 (2001-04-01), Wuu et al.
patent: 6300235 (2001-10-01), Feldner et al.
patent: 6316345 (2001-11-01), Shields
patent: 6326301 (2001-12-01), Venkatesan et al.
Hui Angela T.
Matsumoto David H.
Ramsbey Mark T.
Sun Yu
Advanced Micro Devices , Inc.
Louie Wai-Sing
Pham Long
Winstead Sechrest & Minick P.C.
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