Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-03-22
2003-10-21
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S314000, C257S315000, C257S316000, C257S317000, C257S318000, C257S319000, C257S320000, C257S321000, C257S322000, C257S323000, C257S390000
Reexamination Certificate
active
06635943
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, such as flash memory devices, more particularly to a method and system for removal of the antireflective-coating layer.
BACKGROUND OF THE INVENTION
A conventional semiconductor device, such as a conventional flash memory, includes several layers of components. For example, memory cells in a memory region of the semiconductor device may be in the layer of components on and just above the substrate. Components in subsequent layers should be electrically insulated from components in layers above and below except where electrical connection is specifically desired to be made. The layer that isolates distinct layers is known as the conventional interlayer dielectric (“ILD”). Electrical connection to lower layers is made using conventional contacts which extend through the ILD.
FIG. 1
is a flow chart depicting a conventional method
10
for fabricating a portion of a conventional semiconductor device, such as a conventional embedded flash memory. Components in lower layer are fabricated, via step
12
. For the first conventional ILD, the lower layer is the layer just above the substrate. Thus, step
12
could include fabricating the memory cells in the first layer of the semiconductor device. A conventional ILD consisting of borophospho-tetraethylorthosilicate (“BPTEOS”) or borophospho-silicate glass (“BPSG”) is then provided, via step
14
. Thus, the conventional ILD is typically B and P doped TEOS or a B and P doped silicate glass. Typically, contact is made to various portions of the lower layer through the conventional ILD. Thus, conventional contacts are fabricated, via step
16
. The conventional ILD layer is then planarized, via step
18
. Typically, step
18
includes providing a chemical mechanical polish (“CMP”). Processing of the conventional semiconductor device then continues, via step
20
. Step
20
typically includes fabricating components for subsequent layers and the conventional ILD layers that separate subsequent layers.
FIG. 2
depicts a portion of a conventional semiconductor device
20
after the first ILD
60
is formed. The conventional semiconductor device
20
includes memory cells
30
,
40
and
50
. The memory cells
20
and
30
share a common drain
22
. The memory cells
40
and
50
share a common source
26
. Also depicted are source
24
and drain
28
. The conventional ILD
60
includes conventional contacts
62
and
64
. The memory cells
30
,
40
and
50
include a floating gate
32
,
42
or
52
, respectively, separated from the substrate
21
by a thin insulating layer
31
,
41
or
51
, respectively. The memory cells
30
,
40
and
50
also include a control gate
34
,
44
and
54
, respectively separated from floating gates
32
,
42
, and
52
, respectively by insulating layers
33
,
43
and
53
, respectively. The memory cells
30
,
40
and
50
also include spacers
36
and
38
,
46
and
48
, and
56
and
58
, respectively.
Although the conventional method
10
can be used for fabricating the conventional semiconductor device
20
, one of ordinary skill in the art will readily understand that the conventional method
10
results charge gain and charge loss issues due to the use of BPSG or BPTEOS for the conventional ILD. BPSG and BPTEOS contain boron, which is highly mobile. Because boron is mobile, the conventional ILD
60
can fill gaps such as the space between the memory cell
40
and the memory cell
50
. Thus, boron is used to allow the conventional ILD
60
to fill in gaps, providing a relatively planarized conventional ILD
60
.
Although the presence of boron allows the conventional ILD to fill gaps in the lower layer, the mobility of boron may also allow charge to move through the conventional ILD
60
. As a result, components in the semiconductor device
20
may unexpectedly gain or lose charge. For example, the memory cell
30
,
40
or
50
may gain charge when a user does not desire the memory cell
30
,
40
or
50
to store charge. Similarly, a charge stored on the floating gate of the memory cell
30
,
40
or
50
may leak away when the user desires the memory cell
30
,
40
or
50
to store a charge. For example, a charge intentionally stored on the floating gate
42
may bleed away. The cells
30
,
40
or
50
may be subject to unanticipated charge gain and charge loss. As a result, the cells
30
,
40
or
50
may not function as desired.
Accordingly, what is needed is a system and method for providing the semiconductor device in which the unexpected charge gain and unexpected charge loss are reduced. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device. The method and system comprise providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using only species of relatively low mobility. The method and system also comprise planarizing a surface of the interlayer dielectric.
According to the system and method disclosed herein, the present invention provides an interlayer dielectric which can fill gaps but does not a highly mobile species, such as boron. Consequently, the undesired charge gain and charge loss are reduced.
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patent: 6242299 (2001-06-01), Hickert
patent: 6265294 (2001-07-01), Park et al.
patent: 6300229 (2001-10-01), Tanaka et al.
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patent: 5-259296 (1993-10-01), None
patent: 5-259298 (1993-10-01), None
patent: 11-26725 (1999-01-01), None
Huang Richard J.
Hui Angela T.
Pham Tuan Duc
Ramsbey Mark T.
You Lu
Advanced Micro Devices , Inc.
Flynn Nathan J.
Sefer Ahmed N.
Winstead Sechrest & Minick P.C.
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