Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-12-17
2002-05-14
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S263000, C438S266000
Reexamination Certificate
active
06387755
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor processing and more particularly to a method and system for providing a memory cell having rounded gate edges with reduced gate edge lifting.
BACKGROUND OF THE INVENTION
Conventional flash memory cells include a source, a drain, a channel between the source and drain, and a gate stack. The gate stack includes at least a floating gate and a control gate disposed above the floating gate. Typically, the floating gate and control gate are comprised of polysilicon.
In order to provide a conventional memory cell, a tunnel oxide is typically grown on a semiconductor substrate. The gate stack layers are then deposited and etched to form the gate stack. Typically, an oxidizing step is then performed. Subsequently, source and drain implants can be provided.
The oxidizing step has several functions. After etching, the corners of the floating gate, such as the corner between the side and bottom of the floating gate are sharp. Electric fields are typically significantly stronger near corners of an object. To reduce these fields, the corner should be rounded. The oxidation step rounds these corners of the floating gate. In addition, the edge of the polysilicon forming the control gate and the floating gate is exposed after the gate stack is formed by etching. The oxidation step seals the polysilicon gates to prevent leakage of charge carriers during use.
Although a conventional memory cell formed as discussed above functions, the oxidation of the gate stack also causes the edge of the floating gate to lift. The oxide forms by oxidizing both the polysilicon of the floating gate and the semiconductor beneath the tunnel oxide. In addition to rounding the corner of the floating gate, the oxidation step also oxidizes a portion of the bottom of the floating gate and the semiconductor beneath the floating gate. Thus, a portion of the floating gate near the edge of the floating gate is separated from the underlying semiconductor by a distance greater than near the center of the floating gate. This phenomenon is known as gate edge lifting.
Gate edge lifting affects placement of the source of the conventional memory cell. Conventional memory cells are erased by tunneling of charge carriers between the floating gate and the source. The tunneling depends exponentially on the thickness of the oxide. For a source that is uniformly doped, tunneling occurs where the distance between the floating gate and the source is thinnest. Tunneling also increases with an increase in the dopant concentration in the source. Thus, tunneling occurs where the correct combination of a higher concentration of source dopant and thinner tunnel oxide above the source is found.
Because the gate edge lifts and because tunneling occurs where the tunneling oxide above the source is thinnest, the source of a conventional memory cell must be far enough under the gate to allow for erase despite the gate edge lifting. Thus, in conventional processing, a dopant for the source is driven far under the floating gate to account for the gate edge lifting. For a double diffuse source formed from phosphorus and arsenic, the arsenic is typically driven as far under the gate as possible. As a result, higher temperature drives are used to form the source. Because the correct combination of source dopant concentration and tunnel oxide thickness is difficult to control, erase characteristics of different memory cells may vary.
Because the source of a conventional memory cell must overlap the floating gate far enough to account for gate edge lifting, conventional memory cells must be made larger. It is desirable to decrease the size of conventional memory cells in order to increase the density of memory cells in an area of the semiconductor. However, as the source and drain of a conventional memory cell become closer, short channel effects adversely affect the behavior of the memory cell. For example, the threshold voltage of the memory cell may drop below a desired level, preventing the memory cell from functioning reliably. Thus, the distance between the source and drain should be as wide as possible for a particular floating gate size. Because of gate edge lifting, the source must be driven farther under the gate than would be required in the absence of gate edge lifting.
Accordingly, what is needed is a system and method for providing a memory cell having rounded floating gate corners in which gate edge lifting is reduced. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for providing a memory cell on a semiconductor. The method and system comprise providing an oxide layer on the semiconductor, and providing at least one gate stack disposed above the oxide layer. The at least one gate stack has a corner contacting the oxide layer. The method and system further comprise exposing at least the corner of the at least one gate stack and rounding at least the corner of the at least one gate stack.
According to the system and method disclosed herein, the present invention reduces gate edge lifting while allowing for rounded gate corners, thereby allowing for a decrease in the overlap between the source and the gate stack without sacrificing erase characteristics.
REFERENCES:
patent: 5847427 (1998-12-01), Hagiwara
patent: 5907188 (1999-05-01), Nakajima et al.
patent: 5963806 (1999-10-01), Sung et al.
Luning Scott D.
Thurgate Timothy J.
Chen Jack
Sawyer Law Group LLP
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