Error detection/correction and fault detection/recovery – Pulse or data error handling – Error detection for synchronization control
Reexamination Certificate
2007-06-19
2007-06-19
Lamarre, Guy (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error detection for synchronization control
C714S776000, C714S022000
Reexamination Certificate
active
10674943
ABSTRACT:
A method and system for performing data integrity process is provided. The method includes selecting a cyclic redundancy code (“CRC”) mode from amongst append, validate and keep, and validate and remove mode. If the append mode is selected, then CRC is appended after each data block boundary. A CRC seed value is incremented for each data block providing a unique CRC value for each data block. If validate and keep mode is selected, then CRC accompanying any data is compared to CRC that may have been accumulated. If validate and remove mode is selected, then CRC is first validated and then CRC is removed before data is sent out. The system includes CRC logic that allows firmware running on an adapter to select one of plural CRC modes including append, validate and keep, and validate and remove mode.
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Anand Sanjaya
Bhargava Ashish
Caballero Kathy K.
Chu Kuangfu David
Gandhi Rajendra R.
Alphonse Fritz
Klein O'Neill & Singh, LLP
Lamarre Guy
QLOGIC Corporation
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