Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-05-31
2003-06-17
Nelms, David (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06581192
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital circuit design. More particularly, the present invention relates to method and system for providing a heuristic approach to testing the building blocks or cells for digital circuit design using cell libraries.
2. Description of the Related Art
In digital design, there are basic building blocks referred to as cells which include logic gates such as, for example, AND gates, OR gates, multiplexers and so on, which are placed in cell libraries. For each cell stored in the cell library, the corresponding functionalities for the building block, pin names, pin positions, as well as information related to compatibility with other cells is stored. While the cells are generally configured for their respective intended operation when tested individually, it is often the case that when the cells are combined in a design implementation, the functionality of the cells may not be obtained as intended.
It is possible to test the individual cells separately such that to identify faulty cells or design defects. However, given that design layouts generally use a large number of cells for its implementation, it is often very time consuming to test the cells individually and may be impractical. Moreover, some errors in the cells stored in the cell libraries may not be detected until the final actual layout implementation stage.
SUMMARY OF THE INVENTION
In view of the foregoing, a method of testing a cell library in accordance with one embodiment of the present invention includes retrieving a plurality of cells stored in a cell library, generating a cell matrix including the retrieved plurality of cells, connecting each of the plurality of cells in the cell matrix, and performing connection verification of each connection of the connecting step.
The retrieved plurality of cells may include all stored cells in the cell library.
The generating step may further include retrieving a rule set for the cell matrix, and generating one or more columns of retrieved cells and one or more rows of retrieved cells based on the rule set.
The retrieved rule set may include one or more of information corresponding to a number of allowable cells in a generated row, and information corresponding to the type of retrieved cells for the generated row.
Each of the retrieved plurality of cells may include at least one input port and one output port, and the connecting step connecting each input and output ports of each of the plurality of cells.
The step of performing connection verification may include detecting an error corresponding to one or more of the plurality of cells in the connecting step, and correcting the detected error corresponding to the one or more of the plurality of cells in the cell library.
The detected error may include one of a pin name error corresponding to the one or more of the plurality of cells, a layout scaling error corresponding to the one or more of the plurality of cells, and a timing error corresponding to the one or more of the plurality of cells, and a size error corresponding to a physical size of the one or more of the plurality of cells.
The method may further include the step of updating the cell library based on the connection verification performing step, where the updating step may include the step of storing information corresponding to one or more of the plurality of cells in the cell library.
Additionally, the method may further include implementing a physical layout of a design based on the cell library, performing an error check of the physical layout, where the error check performing step may include the step of executing an electrical rules checker.
The plurality of cells may include one or more of an AND gate cell, an OR gate cell, and exclusive-OR gate cell, and exclusive-NOR gate cell, a flip-flop cell, a multiplexer cell, an adder cell, and a subtractor cell.
Alternatively, the plurality of cells may include one or more of a simple combinational cell and a complex combinational cell.
A method of testing a cell library in accordance with another embodiment of the present invention includes retrieving each cell stored in a cell library, generating a cell matrix including the retrieved cells, connecting each retrieved cell in the cell matrix, detecting an error corresponding to one or more of the retrieved cells in the connecting step, and correcting the detected error corresponding to the one or more of the retrieved cells.
A system for testing a cell library in accordance with yet another embodiment of the present invention includes means for retrieving a plurality of cells stored in a cell library, means for generating a cell matrix including the retrieved plurality of cells, means for connecting each of the plurality of cells in the cell matrix, means for performing connection verification of each connection of the connecting step.
The generating means may include means for retrieving a rule set for the cell matrix, and means for generating one or more columns of retrieved cells and one or more rows of retrieved cells based on the rule set.
Moreover, each of the retrieved plurality of cells may include at least one input port and one output port, and the connecting means configured to connect each input and output ports of each of the plurality of cells.
The means for performing connection verification may include means for detecting an error corresponding to one or more of the plurality of cell, and means for correcting the detected error corresponding to the one or more of the plurality of cells in the cell library.
The system may further include means for updating the cell library based on the connection verification, where the updating means may additionally include storing means for storing information corresponding to one or more of the plurality of cells in the cell library.
Further, in one aspect, the system may also include means for implementing a physical layout of a design based on the cell library, and means for performing an error check of the physical layout. Additionally, the error check performing means may include means for executing an electrical rules checker.
A system for testing a cell library in accordance with still another embodiment of the present invention includes means for retrieving each cell stored in a cell library, means for generating a cell matrix including the retrieved cells, means for connecting each retrieved cell in the cell matrix, means for detecting an error in one or more of the connections, and means for correcting the detected error corresponding to the one or more of the retrieved cells.
In the manner described above, in accordance with the various embodiments of the present invention, a column and row configuration schematic of a test design using all the cells in a given cell library may be generated. In particular, the cells may be classified into different types such as simple combinational cells, complex combinational cells, multiplexers, flip flops, AND gates, OR gates, exclusive-OR gates and so on. In one aspect, the cells of a similar type may be then placed in a column, and after placing all the cells from the cell library into organized columns, interconnections are made at random between two successive columns in the generated column and row configuration. All of the output pins or ports from a particular column and all the input pins or ports on the subsequent column are used up in this process such that all the pins or ports of the cell in the column and row configuration are connected. The input pins on the first column may then effectively become the primary inputs of the resultant test design and the output pins on the last column become the primary outputs of the test design.
With the generated column and row configuration of the test design, the cells are then placed in the regular design cycle which includes placement, routing and backend design checks. If the test design passes all the error verifications when placed in the regular design cycle, then the cells used in the test design from the cell library m
Martine & Penilla LLP
Nguyen Dao H.
Sun Microsystems Inc.
LandOfFree
Method and system for providing a heuristic approach for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for providing a heuristic approach for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for providing a heuristic approach for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3114685