Method and system for performing Viterbi decoding using a...

Details Method and system for performing Viterbi decoding using a... Method and system for performing Viterbi decoding using a...

2011-07-12

2011-07-12

Alphonse, Fritz (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S755000, C714S788000

Reexamination Certificate

active

07979781

ABSTRACT:
A method for performing Viterbi decoding using a reduced trellis memory is provided that includes dividing a block of data into a plurality of segments. A feed-forward process is performed on each of the segments to generate a trellis for each of the segments. A traceback process is performed on each of a plurality of overlapping segment pairs, each segment pair comprising a first segment and a second segment, to generate a traceback result for the first segment and a traceback result for the second segment. The traceback result for the second segment is discarded to generate a decoder output based on the traceback result for the first segment.

REFERENCES:
patent: 6608870 (2003-08-01), Fimoff
patent: 6687310 (2004-02-01), Fimoff et al.
patent: 6871303 (2005-03-01), Halter
patent: 2002/0110183 (2002-08-01), Kaewell, Jr.
patent: 2003/0012290 (2003-01-01), Fimoff et al.

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