Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-07-01
2002-09-17
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06453437
ABSTRACT:
FIELD OF THE INVENTION
The field of the present invention pertains to the testing of integrated circuits. More particularly, the present invention pertains to a method and system for efficiently generating test vectors for use with automated testing equipment (ATE) for testing integrated circuits to detect faults therein.
BACKGROUND OF THE INVENTION
Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Typically, the more powerful and complex the system, the greater its utility and usefulness. However, as these computer and software implemented systems and processes become more powerful, detecting and correcting flaws within the systems becomes increasingly difficult.
Prior art
FIG. 1
shows a diagram of a basic design synthesis process. As depicted in
FIG. 1
, an HDL (hardware description language) netlist
101
, synthesis process
102
, and a completed integrated circuit device
103
are shown. As is well known by those skilled in the art, HDL representations (e.g., represented one or more levels of abstraction) are used by engineers to model the expected behavior and functionality of a desired device. Once the HDL representation is “verified”, it is processed by an HDL compiler program to produce HDL netlist
101
, which comprises a detailed list of logic components and the interconnections between these components for implementing the behavior and functionality. HDL netlist
101
then undergoes computer aided design synthesis process
102
, wherein the components comprising HDL netlist
101
are mapped to specific technology libraries to convert the technology independent logical representation (HDL netlist
101
) into standard circuits and other required information for fabrication of the resulting device. As depicted in
FIG. 1
, the result of CAD synthesis process
102
is the completed integrated circuit device
103
.
Prior art
FIG. 2
shows two diagrams of commonly encountered manufacturing defects within fabricated integrated circuit devices. Diagram
201
shows a “short” defect between a first line
210
and a second line
211
. A short defect occurs when, for example, a contaminant particle (e.g., dust, etc.) causes extraneous metal deposit
215
to occur across lines
210
and
211
. Metal deposit
215
thus electrically shorts lines
210
and
211
, disrupting the functionality that depends upon these two lines. Diagram
202
shows an “open” defect between line
210
and
211
. And open defect occurs when, for example, a contaminant particle causes and inadvertent discontinuity
220
during the deposition of one or more metal lines. Discontinuity
220
disrupts the functionality that depends upon line
210
.
Thus, any integrated circuit devices including defects such as shorts or opens shown in diagrams
201
and
202
are most likely defective, and must be caught before the devices are shipped to customers. Very sophisticated test programs, automatic test pattern generation (ATPG) programs, are used to analyze the various netlist representative of the integrated circuit designs (e.g., HDL netlist
101
) and generate therefrom the test patterns (e.g., also referred to as test programs or test vectors) used for testing the devices with automated test equipment (ATE) systems.
The ATPG process is designed to facilitate the detection of defective integrated circuit devices. An integrated circuit device is defective if it includes one or more defects, or flaws within its internal circuitry, which interfere with its proper functionality. The most advanced manufacturing processes produce large numbers of defective devices along with nominal devices. A typical yield for an advanced manufacturing process is, for example, 70 percent, wherein 70 percent of the fabricated devices are nominal and 30 percent of them are defective. The goal of ATPG is to create test vectors for use with ATE systems which will always identify a defective device. The test vectors thereby ensure end product quality, wherein the only devices which are shipped to customers are the nominally performing, defect free integrated circuit devices.
Unfortunately, circuit level defects like shorts and opens are very difficult to generate tests for, even with the most sophisticated ATPG programs. In automatic test program generation analysis, it is extremely difficult to deterministic ally analyze a netlist representation with sufficient detail to detect individual shorts or opens on individual circuits. Modern devices typically include many millions of individual circuit elements (e.g., transistors, interconnects, etc.). At this lowest level, large modern devices cannot be efficiently analyzed via ATPG.
Thus, for efficiency reasons, ATPG is mostly done at the gate level (AND gate, OR gate, etc.) and higher. In most devices, each gate is typically implemented using 4 to 5 transistors. The problem is that the higher the level at which ATPG is done, the further away from the actual circuit level defect (e.g., defect
215
and
220
) the testing is being performed. Because of this, even though a defect may be a simple short or open, at the higher levels of testing, the defect may manifest itself differently, often in subtle, hard to detect ways. Hence, ATPG at higher levels (e.g., gate level and above) involves modeling the behavior of the defects as manifested at the higher level, and then generating tests designed to detect the specific manifestation of that behavior.
To perform ATPG, the ATPG program tests for “faults” which are models of defects. The ATPG program models the behavior of certain faults and then tests for the occurrence of that behavior. The faults are designed to abstract the physical manifestation of the real defects. The faults should match the behavior and manifestation of the real defects at the end, when a particular finished device is actually tested.
There are many different types of defect fault models, fault and fault model in use in ATPG processing. “Stuck-at” faults are the most commonly used. Stuck-at faults match a certain set of real defects which occur in fabricated integrated circuit devices. As is well known, stuck-at faults consider lines between gates to be “stuck at” logical zero “0” or logical one “1” (e.g., short to Add or Gnd). Stuck-at fault Tests detect those defects which manifest themselves as interconnect lines being always at one or zero regardless of the overall state of the device.
There is a problem, however, in that stuck-at faults do not match all defects, hence test patterns devised for them do not catch all defective devices. To catch more of the remaining defects, other alternative fault models are also used in addition to stuck-at faults. The most commonly used alternative fault model is typically the “transition” fault model. Transition faults are similar to stuck-at faults, however, instead of being stuck at logical zero or logical one, a defective line is slow to rise or slow to fall to logical one or zero. Thus adding a temporal aspect to the fault model.
Transition faults add a timing aspect to the stuck-at fault model. For example, the timing aspect of transition faults detects slow-to-rise and slow-to-fall defects wherein the line is not stuck at for example zero, but rises to logical one too slowly, causing a signal failure. Whereas stuck-at faults assume a line is fixed at a certain level (one or zero), transition faults test for and are capable of finding slow-to-rise and slow-to-fall defects because of the timing aspects.
Even with the use of both stuck-at faults and transition faults, prior art ATPG does not catch all defective devices. Because of the timing aspect differences, stuck-at faults and transition faults are not easily combined within typical prior art ATPG tools. The heuristics used to determine test patterns for stuck-at faults are non-optimal for the test patterns of transition faults. Because of this, the quality of testing suffers, the testing process itself is less efficient, and the likelihood of defective devices being shipped to customer
Kapur Rohit
Waicukauski John
Williams Thomas W.
Wohl Peter
Chase Shelly A
De'cady Albert
Synopsys Inc.
Wagner , Murabito & Hao LLP
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