Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-07-20
2001-05-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S019000
Reexamination Certificate
active
06230302
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and system for integrated circuit design in general and, in particular, to an automated method and system for integrated circuit design. Still more particularly, the present invention relates to an automated method and system for performing timing analysis on an integrated circuit design.
2. Description of the Prior Art
Logic synthesis has now become an integral part of an integrated circuit (IC) design automation process. A logic synthesis system typically contains various analysis programs (or analysis tools), each intended for achieving a different purpose, such as logic design, circuit area targeting, timing and delay analysis, etc. These analysis programs play an important role in the design automation process, both in their own right as well as part of a logic synthesis system that utilizes them to evaluate the quality of various synthesized circuits extracted from the IC design.
Generally speaking, a timing analysis program analyzes the temporal behavior of an IC design by determining when a timing event occurs within the IC design. For example, in a synchronized digital system design, the timing analysis program is utilized to determine the delay of a combinational part of an IC design. The delay of the combinational circuit is the time taken for the outputs of the combinational circuit to settle at a final value after the inputs have been applied. This delay, in turn, is utilized to determined the minimal permissible clocking period of the entire digital system design.
Before timing analysis is performed, RC delays and capacitance on an IC design are calculated on a per net basis by an IC design extraction program. The results from such calculation are then fed into a timing analysis program such that various cycle times of the IC design can be determined. One problem with the prior art timing analysis programs is that they typically take an extensive amount of time to generate a complete set of physical data for the entire IC design. Thus, most circuit designers often defer the full-cycle of creating the complete set of physical data in order to gain extra design time. Even though such a solution may be acceptable at times, it is always advantageous to be able to conveniently perform a timing analysis on the entire IC design in order to gain more accurate timing information about the design at any stage of the design process. Hence, it would be desirable to provide an improved method and system for performing timing analysis on an IC design in order to facilitate the IC design automation process.
SUMMARY OF THE INVENTION
In view of the foregoing, it is therefore an object of the present invention to provide an improved method and system for designing integrated circuits.
It is another object of the present invention to provide an improved automated method and system for integrated circuit design.
It is yet another object of the present invention to provide an improved automated method and system for performing timing analysis on an integrated circuit design.
In accordance with a method and system of the present invention, a set of circuit data is extracted from an integrated circuit design. For a number of network within the set of circuit data, a determination is made as to whether or not design criteria are met. For the networks within the set of circuit data, a set of timing parameters is selectively altered if the design criteria are not met. Finally, a timing analysis is performed on the set of circuit data utilizing the selectively altered set of timing parameters.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5367469 (1994-11-01), Hartoog
patent: 5764531 (1998-06-01), Kojima et al.
patent: 5787008 (1998-07-01), Pullela et al.
patent: 5845233 (1998-12-01), Fishburn
patent: 5896300 (1999-04-01), Raghavan et al.
patent: 5933356 (1999-08-01), Rostoker et al.
patent: 6009248 (1999-12-01), Sato et al.
patent: 6023568 (2000-02-01), Segal
Gupta et al. (“The Elmore delay as a bound for RC trees with generalized input signals”, IEEE Transactions on Computer-Aided Design of integrated Circuits and Systems, vol. 16, No. 1, Jan. 1997, pp. 95-104), Jan. 1997.*
Fernandez et al. (“Clock period optimization in a multiphase edge-clocked circuit constrained to a maximum number of phases”, Proceedings of the 23rd Euromicro Conference on New Frontiers of Information Technology Short Contributions, EUROMICRO 97, Sep. 1, 1997.
Gabele Carol Ivash
Patel Parsotam Trikam
Quay Stephen Thomas
Spencer Alexander Koos
Villarrubia Paul Gerard
England Anthony V.S.
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
Kik Phallaka
Smith Matthew
LandOfFree
Method and system for performing timing analysis on an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for performing timing analysis on an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for performing timing analysis on an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2553004