Method and system for performing memory repair analysis

Details Method and system for performing memory repair analysis Method and system for performing memory repair analysis

2001-11-20

2004-06-15

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S718000

Reexamination Certificate

active

06751760

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a memory repair analysis (MRA) system and a method for performing memory repair analysis, particularly to a method for testing and repair analyzing semiconductor memories by using a merge circuit.
BACKGROUND OF THE INVENTION
Conventionally, memories such as dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, double data rate DRAM (DDR DRAM), or system of chip (SOC) including memories are made by semiconductor manufacturing processes. For example, a plurality of DRAM memory dies (the number is from hundreds to few thousands) are formed on a wafer with integrated circuits, such as a wafer of 6 inches, 8 inches, or 12 inches. However, according to small-sized and complicated trends of electronic elements, and advanced manufacturing technique, memory capacity is synchronously increased, such as familiar DRAM of 4 Mb or 16 Mb has been increased up to DRAM of 64 Mb, 128 Mb or 256 Mb, even DDR DRAM.
When memory capacity becomes bigger and bigger, it is inevitable that the possibility of generating fail memory cells in the semiconductor manufacture becomes higher. Yield of good known dies would decrease on a wafer as the number of fail memory devices increases. Therefore, memory device has not only a memory region of normally grouping rows and columns, but also a redundancy circuit (or called redundancy cells). The fail memory cells in the normal region are replaced by redundancy cell by using the technique of laser repair to change electric circuit paths for enhancing product yield.
For the semiconductor manufacturing process of memories, the technique of memory repair analysis (MRA) has to be used in testing and repairing (laser or high voltage melting) operations. The MRA process is performed in order to repair memory cells properly, includes: taking the information of location and counting of fail cells by testing, analyzing and identifying if the fail cells are repairable or not and how to replace if they are repairable in order to proceed next repairing processes.
U.S. Pat. No. 5,841,783 entitled “Fail Address Analysis And Repair System For Semiconductor Test” has disclosed a memory repair analysis system. As shown in FIG.
1
,. the system comprises a semiconductor testing equipment
150
, a repair address analysis apparatus
160
, and a testing equipment control unit
170
. Testing equipment control unit
170
serves as a control interface between semiconductor testing equipment
150
and repair address analysis apparatus
160
. Semiconductor testing equipment
150
includes a fail memory
151
for storing fail bits information of a memory device and a control unit
152
for controlling fail memory
151
. Repair address analysis apparatus
160
includes a fail buffer memory
161
for storing the information transferred from fail memory
151
to repair address analysis apparatus
160
, a fail count unit
162
for analyzing the information in fail buffer memory
161
to be repair information, and a control unit
163
for controlling fail buffer memory
161
and fail count unit
162
.
In the familiar memory repair analysis system mentioned above, when a fail bit is identified in a memory device by semiconductor testing equipment
150
, the information of a fail bit will be stored into fail memory
151
by control unit
152
. Then, before proceeding next functional test by semiconductor testing equipment
150
, the information stored in fail memory
151
must be transferred and stored into fail buffer memory
161
of repair address analysis apparatus
160
. However, with skilled and complicated trends of memory devices, a memory device needs to be executed for multiple and different functional tests. It is necessary to transfer the data of fail bit from fail memory
151
of semiconductor testing equipment
150
into fail buffer memory
161
of repair address analysis apparatus
160
after each functional test, then performing a long-time and improper memory repair analysis (MRA). Besides, semiconductor testing equipment
150
must wait to transfer data of fail bit until repair address analysis apparatus
160
finishes analyzing operation, so that it will cause a slow testing speed. It is a waste of time operating several memory repair analysis (MRA) processes for each memory device, so that it is not efficient and economic for very expensive testing and repair analysis facilities.
SUMMARY
It is a main object of the present invention to provide a method for testing and repair analyzing semiconductor memories to collect and merge the multiple functional test data of a memory into a merged functional test data of fail bits by using a merge circuit. Then, repair analysis processes would be continued for shortening test time and enhancing test efficiency.
It is another object of the present invention to provide a memory repair analysis system having a merge circuit to collect and merge the address information of fail bits from multiple functional tests executed by a semiconductor testing equipment, and transmit the merged information to a repair address analysis apparatus.
In order to attain the object described above, according to the present invention, multiple functional tests are executed on a memory to obtain the data with addresses of fail bits after each functional test. The data with addresses of fail bits in each functional test are compared with the merged data with addresses of fail bits obtained from previous functional tests and both of two data further is merged. A repair analyzing operation is executed according to the merged data with addresses of fail bits to determine if the memory is repairable and how to repair repairable memory by redundancy circuit.


REFERENCES:
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patent: 5111402 (1992-05-01), Brooks et al.
patent: 5410687 (1995-04-01), Fujisaki et al.
patent: 5841783 (1998-11-01), Suzuki et al.
patent: 5983372 (1999-11-01), Fujiwara
patent: 6618682 (2003-09-01), Bulaga et al.
patent: 6678623 (2004-01-01), Koyama

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