Method and system for performing a double pass NTH fail...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C714S719000

Reexamination Certificate

active

07930602

ABSTRACT:
A method for performing a double pass nthfail bitmap of a memory array of a device under test includes a memory built-in test (MBIST) unit reading previously written data from each location of the memory array during a first pass, and detecting a failure associated with a mismatch between written and read data at each location. The method also includes storing within a storage, an address corresponding to a current failing location in response to determining that a predetermined number of locations have failed. The method further includes the MBIST unit reading the previously written data from each location during a second pass. The method includes locking and providing for output, read data stored at a current read address in response to a match between the current read address and any address stored within the storage.

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patent: 2006/0248414 (2006-11-01), Dubey

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