Method and system for optimizing testing of memory stores

Details Method and system for optimizing testing of memory stores Method and system for optimizing testing of memory stores

2008-04-08

2008-04-08

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S710000

Reexamination Certificate

active

07356744

ABSTRACT:
One embodiment of the present invention keeps a record of memory accesses by an operating system. The records can indicate which memory locations do not need to be checked in a later test. In one embodiment, memory blocks that have been accessed since a predetermined time are not checked in a later memory test. This reduces the time required for the later memory test.

REFERENCES:
patent: 6216226 (2001-04-01), Agha et al.
patent: 6374353 (2002-04-01), Settsu et al.
patent: 6434696 (2002-08-01), Kang
patent: 6647479 (2003-11-01), Laws
patent: 7162625 (2007-01-01), Stern et al.

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