Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2000-07-12
2002-07-16
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S311000, C430S314000, C430S322000, C430S325000, C430S330000, C355S027000, C396S611000, C414S935000
Reexamination Certificate
active
06420098
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method and a system for manufacturing semiconductor devices on a wafer. In particular, though not exclusively it relates to the technique of forming structures on a wafer surface with deep ultraviolet (deep UV) photoresists.
BACKGROUND OF THE INVENTION
It is well known in the art that patterned photoresist masks being removed during normal non-oxide film etching cause poor mask replication onto the wafer. Patterned deep UV (DUV) photoresist is subject to loss of critical dimensions (CD loss) and thickness reduction during etch operations due to resist erosion (thickness loss) and faceting (profile change). Even resists that have been hardbaked (hotplate or UV cure) can have this problem, and this can be critical in metal and polysilicon layer etches.
The reason is that DUV resists have lower etch resistance than conventional resists. During exposure and post expose bake of DUV resists, acid molecules are generated, which then cleave functional groups off the polymer chain, allowing the resist to be developed. Upon the post exposure bake (PEB) process a DUV resist can lose from 8 to 30% of thickness by volume due to decomposition of the photoresist. This same reaction occurs in a plasma etch chamber, in addition to loss of volume by reaction with etchant gases such as chlorine, and subsequent removal of mass.
Another well known feature of UV resists is that DUV photoresist formulations are sensitive to ammonia or amine chemical poisoning (e.g. from ambient environment) that causes the resist to become less sensitive to lithography exposure and insoluble to developer solutions. This effect is called T-topping, in which the resist reacts with the ammonia/amine chemical (not surface limited—the depth of the reaction is somewhat dependent on the time exposure and concentration) prior to exposure or developing steps. This poisoning also causes loss of profile and critical dimensions in the resultant printed features with as little as 3 ppb concentrations.
In prior art processes UV hardening is combined with chemical poisoning in a standalone tool. In particular photoresist sensitivity to ammonia/amine chemical poisoning and using chemical exposure to make the resist more stable/resistant is known in the art (PRIST). Using the ammonia/amine chemical poisoning to improve etch/implant or liquid processing has been disclosed and presented in the prior art.
Moreover, there are additional gases or vapors that are known to create similar benefits in resists by adding mass (not poisoning) by chemical bonding to the surface. These different chemicals can shrink resist features (trimming) or cause them to swell compensating for mask or etch biases.
However, both the additional pre-treatment of the UV resist by UV cure before baking as well as the treatment of the wafer with a dedicated reactive gas as preparation of the UV resist corresponds to a separate step and tool in processing the wafer, which is time consuming and expensive.
The present invention seeks to streamline and condense processing of wafers, to shorten the overall processing time and to reduce the tools to a minimum necessary number.
A specific embodiment of the invention will now be further described, by way of example only, with reference to the accompanying drawings.
REFERENCES:
patent: 3904492 (1975-09-01), Rich et al.
patent: 4988609 (1991-01-01), Hashimoto et al.
patent: 5219791 (1993-06-01), Freiberger
patent: 5667942 (1997-09-01), Nakao et al.
patent: 5692070 (1997-11-01), Kobayashi
patent: 5932380 (1999-08-01), Yaegashi et al.
patent: 6022672 (2000-02-01), Ikeda
patent: 6057084 (2000-05-01), Mohondro
patent: 6100015 (2000-08-01), Yamana
Barreca Nicole
Huff Mark F.
King Robert L.
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