Method and system for managing timing error information

Details Method and system for managing timing error information Method and system for managing timing error information

1999-11-01

2002-10-29

Tu, Christine T. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06473874

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a timing error information managing method and a system, suitable for management of information on timing errors obtained through a timing check of a logical circuit in the process of design of a circuit such as an integrated circuit.
(2) Description of the Related Art
In the process of design of a circuit such as an integrated circuit, for confirming whether or not a logical circuit designed satisfies design requirements, a timing check has commonly been made through the use of a simulator, a timing analysis tool or the like to verify whether or not the time of the occurrence of an event given to a clock input terminal or data input terminal of a flip-flop of the logical circuit meets timings on a setup time and a hold time to be required in the flip-flop.
Furthermore, not only the timing error information obtained through such a timing check using the simulator or the timing analysis tool is put to use for the evaluation on the presence or absence of an error the designer makes personally, but also it is used to set a constraint for delay adjustment as disclosed in Japanese Patent Laid-Open (kokai) No. HEI 4-273581, and even it is employed for displaying an error spot emphatically through the use of a graphic display tool for circuit diagrams or the like.
The timing error information obtained through this timing check generally includes information on the start and end points of a timing check interval (section), an error type (a setup error, a hold error), an error quantity, and others. This timing error information is subjected to retrieval or the like in a manner that the start or end point serves as a key, and used for selecting and grouping errors due to the same clock, for collecting them at every start or end point, or for putting them in order by rearranging in the order of decreasing error quantity, before being put to use for the delay adjustment or the like.
Meanwhile, in general, in such a conventional timing error information managing method, of the timing error information to be obtained as the result of the timing check, a name of an element, a terminal or the like is used as the information which shows the start point or the end point of the timing check interval.
In addition, in recent years, the improvement of design engineering has caused the scale enlargement of an integrated circuit and the complication of its configuration, and a hierarchically designing technique has frequently been taken to accomplish the circuit design in subdivided units.
FIG. 10
illustratively shows one example of configuration of an integrated circuit. In
FIG. 10
, a circuit, denoted generally at numeral
300
, has a hierarchical structure comprising three hierarchies (layers) A to C, and, for example, in designating the position of an element X on the hierarchy C of this circuit
300
, the name of that element follows the names of the hierarchies described successively, like “A. B. C. X”.
However, the actual integrated circuit design needs to handle circuits each having hierarchies exceeding
10
in number in many cases and to cope with complicated names of hierarchies or elements. In fact, a name consisting of more than 100 letters frequently appears at the start or end point of the timing check interval.
Thus, in such a conventional timing error information managing method, since a long name is used as the start or end point of the timing check interval, particularly, in the case that a large volume of timing error occurs, it takes a long time to retrieve or rearrange the timing error information, obtained through a simulation or the like, in a manner that its start or end point is used as a key, which deteriorates the designing efficiency.
SUMMARY OF THE INVENTION
The present invention has been developed in consideration of this problem, and it is therefore an object of this invention to provide a timing error information managing method and a system which are capable of managing timing error information with high efficiency to speed up various types of processing through the use of the timing error information.
For this purpose, in accordance with this invention, there is provided a timing error information managing method of managing information on timing errors located through a timing check of a circuit, comprising a step of reading a timing error information file storing the information on the timing errors and a circuit information file storing information on configurations of the circuit to establish a correlation between each of the timing errors in the timing error information file and each of the circuit configurations in the circuit information file, a step of adding to the timing error information file a circuit information pointer for giving an instruction regarding a position of the storage of the information on the circuit configuration, causing each of the timing errors, in the circuit information file, a step of adding to the circuit information file an error information pointer for giving an instruction regarding a position of the storage of the information on the timing error, occurring in each of the circuit configurations, in the timing error information file, and a step of managing the information on the timing errors through the use of the circuit information pointer and the error information pointer.
Furthermore, in accordance with this invention there is provided a timing error information managing system for managing information on timing errors located through a timing check of a circuit, comprising a timing error information file storing the information on the timing errors, a circuit information file storing information on configurations of the circuit, a correlating section for establishing a correlation between each of the timing errors in the timing error information file and each of the circuit configurations in the circuit information file and for adding to the timing error information file a circuit information pointer for giving an instruction regarding a position of the storage of the information on the circuit configuration, causing the occurrence of each of the timing errors, in the circuit information file and further for adding to the circuit information file an error information pointer for giving an instruction regarding a position of the storage of the information on the timing error, occurring in each of the circuit configurations, in the timing error information file, and a managing section for managing the information on the timing errors through the use of the circuit information pointer and the error information pointer.
Accordingly, in the timing error information managing method and system according to this invention, through the retrieval of the circuit information file, the error information pointer indicates the storage position of the correlating timing error registered in this circuit information file, which, even if a large quantity of timing error exists, allows a retrieval of the timing errors to be made at a high speed in response to a retrieval request so that the timing error information can be managed with high efficiency.


REFERENCES:
patent: 4314331 (1982-02-01), Porter et al.
patent: 5231638 (1993-07-01), Fujiki
patent: 5390318 (1995-02-01), Ramakrishnan et al.
patent: 6308305 (2001-10-01), Sugiyama et al.
patent: 4-273581 (1992-09-01), None
patent: 8-221456 (1996-08-01), None

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