Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-02-03
2001-05-22
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S744000
Reexamination Certificate
active
06237119
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to electronic devices and, in particular, to communication between electronic devices. Still more particularly, the present invention relates to a method and system for communicating input/output (I/O) signals via address lines of an interconnect linking electronic devices.
2. Description of the Related Art
Debugging a highly integrated, complex integrated circuit (e.g., an Applicant Specific Integrated Circuits (ASICs)) is difficult due to the limited visibility of the internal states of the integrated circuit. In order to make such internal states available for external observation, many conventional integrated circuits are equipped with dedicated debug I/O pins on which the states of selected internal testpoints are made visible. However, increasing the number of I/O pins can dramatically increase the overall cost of the integrated circuit. The present invention therefore recognizes that it would be desirable and useful to make the internal testpoint states of an integrated circuit available for external observation without the addition of dedicated debug I/O pins.
SUMMARY OF THE INVENTION
A system includes a first integrated circuit and a second integrated circuit coupled by an interconnect including at least one signal line. The first integrated circuit outputs on the signal line an interleaved output signal including both operating data and debug data. The second integrated circuit receives as an input signal, of the operating data and the debug data, only the operating data. In this manner, the internal states of the first integrated circuit are made visible during normal operation of the system without the use of dedicated I/O pins.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5361249 (1994-11-01), Monastra et al.
patent: 6157206 (2000-12-01), Taylor et al.
Bracewell & Patterson L.L.P.
Chung Phung M.
International Business Machines - Corporation
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