Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-02-01
2002-03-12
Ray, Gopal C. (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S025000
Reexamination Certificate
active
06357020
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to computer information handling test systems and more particularly to techniques for computer hardware verification for a single processor or in multiprocessor (“MP”) computer systems. Still more particularly, the present invention relates to sequentially testing for validity of a processor, memory sub-system, system bridge and input/output ports using a Test nano Kernel for architecture and hardware implementation.
2. Description of the Related Art
Most system designs having processors are represented by a model written in some hardware description language (“HDL”) that can be later transformed into silicon. The pre-silicon model is extensively verified through simulation before it is fabricated (“taped-out”). Since the fabrication process is very expensive, it is necessary to keep the number of tape-outs to a minimum by exposing all bugs either in simulation or in early releases of the hardware. While software simulators are slow, they permit unrestricted use of checker probes into the model-under-test. As a result, any violation exposed during simulation can be detected via the probes. On the other hand, hardware exercise programs can run at a very high speed and thus increase test coverage but their checking abilities are limited to the data observed in the test case.
Therefore, the validation of multiprocessor (“MP”) computer systems may be accomplished with the use of several tools and mechanisms utilizing hardware exercise programs. Referring to
FIG. 1
, one such validation cycle
10
is shown utilizing four tests to implicitly validate a multiprocessor system. These tests consist of a bring-up driver microcode
12
, Hardware Test Exerciser (HTX)
14
, firmware
16
, and Operating Systems
18
(i.e. AIX) tests, as shown in FIG.
1
. However, microcode
12
, firmware
16
and operating systems
18
do not execute tests for the processor alone, but for the system. On the other hand hardware test exercisers
14
require that operating systems
18
be installed and operational prior to loading and execution because it runs on top of operating systems
18
. Moreover, these hardware excercisers
14
tests run too late in the test cycle to be useful as a processor verification tool. By way of example, but not of limitation, HTX
14
and AIX
18
will be used throughout as types of hardware test exerciser and operating system.
Additionally, in some cases, the AIX
18
is not ready to implement certain hardware functions further limiting the HTX
14
capabilities and given the size of HTX
14
and AIX
18
, HTX
14
is considered bulky for processor verification. Lastly, due to the complexity of porting AIX
14
and HTX
18
, the software walks through the hardware before it gets to the primary task of the present invention, which is processor verification.
It would be desirable, therefore, to provide a method and system for a test tool that will stress and test a processor in a multiprocessor system very early in the development cycle. Additionally, it would be desirable for the test tool to run without the production operating system to reduce the dependency of the hardware on the operating system for hardware verification and vice versa. Furthermore, it would be desirable for the test tool to operate with or without I/O and memory requirements and be able to run from the cache alone. It would also be desirable to have an operating system with the ability to hand over the control to the test case and get it back in an orderly fashion without restricting the test case scope. The subject invention herein solves all of these problems in a new and unique manner which has not been part of the art previously.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide a method and a means for hardware verification for a single processor or multiprocessor systems.
It is another object of the present invention to provide a method and system that will stress and test a processor very early in a development cycle utilizing a very small amount of software code.
It is yet another object of the present invention to provide a method and system for a Test nano Kernel that may perform sequential validity tests for a processor, memory sub-system, system bridge and input/output ports.
The foregoing objects are achieved as is now described. The method and system of the present invention provides for a test tool consisting of a Test nano Kernel and supported test programs (exercisers) which sequentially stage stress or validity tests for the central complex electronics hardware for architecture and hardware implementation for a single processor or in a multiprocessor system. Central electronics complex hardware is a processor, memory sub-system and system bridge coupled together and may include the input/output ports. Each stage becomes increasing complex as the hardware platform becomes more stable. The Test nano Kernel requires approximately 500 K of memory or cache to operate, provides multi processor support and implements context and 64-bit execution, interrupt vector ownership, effective equal to real and shared memory service, segment register attachment, gang scheduling and CPU affinity services over and above the major subset of standard UNIX functions. The Test nano Kernel provides for a smooth transition from simulation due to its capabilities to run simulation test cases on real hardware.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description. Kernel provides for a smooth transition from simulation due to its capabilities to run simulation test cases on real hardware.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Bohizic Theodore Joseph
Kapoor Shakti
Kobrosly Walid M.
Bracewell & Patterson L.L.P.
Henkler Richard A.
Leeuwen Leslie A. Van
Ray Gopal C.
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