Method and system for interfacing a plurality of memory...

Details Method and system for interfacing a plurality of memory... Method and system for interfacing a plurality of memory...

2008-02-20

2010-11-09

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus expansion or extension

C710S305000, C710S308000, C710S312000

Reexamination Certificate

active

07831755

ABSTRACT:
A method for establishing an interface between a host and a plurality of memory devices of a system that utilizes a Multimedia Card (MMC) or Digital (SD) protocol according to an interleaving scheme. A host sequentially transmits a first sequence of commands and data to a system bus in order to allow a first memory device among the memory devices to perform a first operation. The host then transmits a second sequence of commands and data to the system bus to allow a second memory device among the memory devices to perform a second operation after transmitting the first sequence of commands and data.

REFERENCES:
patent: 7162569 (2007-01-01), Conley et al.
patent: 2004/0064612 (2004-04-01), Pinto et al.
patent: 2006/0218324 (2006-09-01), Zayas
patent: 2007/0033334 (2007-02-01), Katayama et al.
patent: 05342095 (1993-12-01), None
patent: 200481449 (2004-09-01), None
patent: 20050110609 (2005-11-01), None

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