Method and system for integrating SRAM and DRAM architecture...

Details Method and system for integrating SRAM and DRAM architecture... Method and system for integrating SRAM and DRAM architecture...

2011-06-14

2011-06-14

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S128000, C711SE12043

Reexamination Certificate

active

07962695

ABSTRACT:
A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining whether a memory access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether LRU way of the first type memory structure is also the LRU way of the entire congruence class, and if not, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and filling the LRU way of the first type memory structure with a new cache line in the event of a cache miss; and updating LRU bits, depending upon the results of the memory access request.

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