Method and system for inferring fault propagation paths in...

Details Method and system for inferring fault propagation paths in... Method and system for inferring fault propagation paths in...

2005-02-15

2005-02-15

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06857094

ABSTRACT:
Disclosed is a system for inferring faulty locations in a combinational logic circuit by tracing a fault propagation path from a faulty terminal through repetition of logic decisions and implications. The system infers a logic state by repeating logic state decisions and implications and comparing the logic state with an expected value, which corresponds to a normally operating logic state, thereby inferring a fault propagation path in the logic circuit. The system includes decision-limit discrimination circuitry for providing an upper limit on a decision level that represents a number of logic state decisions and, if the number exceeds the upper limit, for switching the logic state decision to simple retrieval of a fault propagation path, and simple retrieval circuitry for extracting a fan-in cone by tracing a net list of the logic circuit in an input direction from an undetermined gate whose output signal is faulty and whose input/output signal lines have a signal line the logic state of which is unknown, and registering, as fault propagation paths, signal lines which are included in the fan-in cone.

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