Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-16
2007-01-16
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S016000
Reexamination Certificate
active
10904413
ABSTRACT:
A method for an incremental behavioral validation of a digital design expressed in a hardware description language includes: receiving a design expressed in HDL code; providing a user interface permitting a designer to insert special comments into the received HDL code; using the special comments to identify testable parts of the design; creating a demonstration sequence for a testable part; performing a behavioral simulation of the testable part and applying the demonstration sequence at inputs of that part to drive the simulation; displaying the results of the simulation via the user interface by observing outputs of the simulated testable part, permitting the designer to determine whether the testable part implements the requirements of an informal specification; modifying the HDL design to correct designer identified failures; and selecting a next testable part and continuing until all testable parts correctly implement the designer's understanding of the informal specification.
REFERENCES:
patent: 5701443 (1997-12-01), Oguma et al.
patent: 5809283 (1998-09-01), Vaidyanathan et al.
patent: 5910897 (1999-06-01), Dangelo et al.
patent: 5933633 (1999-08-01), Good et al.
patent: 5987442 (1999-11-01), Lewis et al.
patent: 6141630 (2000-10-01), McNamara et al.
patent: 6175946 (2001-01-01), Ly et al.
patent: 6209120 (2001-03-01), Kurshan et al.
patent: 6216252 (2001-04-01), Dangelo et al.
patent: 6292765 (2001-09-01), Ho et al.
patent: 6321363 (2001-11-01), Huang et al.
patent: 6366874 (2002-04-01), Lee et al.
patent: 6446243 (2002-09-01), Huang et al.
patent: 6490711 (2002-12-01), Buckley
patent: 6594804 (2003-07-01), Hojati
patent: 6698002 (2004-02-01), Chang et al.
patent: 7089517 (2006-08-01), Yamoto et al.
patent: 2001/0025369 (2001-09-01), Chang et al.
patent: 2002/0032889 (2002-03-01), Ghosh
patent: 2002/0059054 (2002-05-01), Bade et al.
patent: 2002/0078424 (2002-06-01), Buckley, Jr.
patent: 2003/0135832 (2003-07-01), Buckley, Jr.
patent: 2005/0010880 (2005-01-01), Schubert et al.
patent: 2005/0022086 (2005-01-01), Kotz et al.
Pietro et al., “Generation of Execution Sequences for Modular Time Critical Systems”, IEEE Transactions on Software Engineering, vol. 26, No. 2, Feb. 2000, pp. 128-149.
Y.-C. Hsu, et al., “Advanced Techniques for RTL Debugging,” Proc. Des. Auto. Conf.,2003, pp. 362-367.
C.-N.J. Liu, et al., “An Automatic Controller Extractor for HDL Descriptions at the RTL,” IEEE Des. Test Comp., Jul.-Sep. 2000, pp. 72-77.
L. Zhang, et al., “Automatic Design Validation Framework for HDL Descriptions via RTL ATPG,” Proc. 12th Asian Test Symp., 2003.
I. Ghosh, et al., “On Automatic Generation of RTL Validation Test Benches Using Circuit Testing Techniques,” GLSVLSI'03, Apr. 28-29, 2003, pp. 289-294.
R.E. Bryant, “A Methodology for Hardware Verification Based on Logic Simulation,” Jour. ACM, vol. 38, No. 3, Apr. 1991, pp. 299-328.
T.-H. Wang, et al., “Practical FSM Analysis for Verilog,” Int'l Verilog HDL Conf. and VHDL Int'l Users Forum, Mar. 1998, pp. 52-58.
K.-T. Cheng, et al., “Automatic Generation of Functional Vectors Using the Extended Finite State Machine Model,” ACM Trans. Des. Auto. Elec. Sys., vol. 1, No. 1, Jan. 1996, pp. 57-79.
Buckley Robert
Kik Phallaka
Yardstick Research, LLC
LandOfFree
Method and system for incremental behavioral validation of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for incremental behavioral validation of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for incremental behavioral validation of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3730163