Method and system for improving the topography of a memory...

Details Method and system for improving the topography of a memory... Method and system for improving the topography of a memory...

2007-06-05

2007-06-05

Smoot, Stephen W. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S294000, C438S926000

Reexamination Certificate

active

10861575

ABSTRACT:
A method and system for improving the topography of a memory array is disclosed. In one embodiment, a dummy bitline is formed over a field oxide region at an interface between a memory array and interface circuitry. In addition, a poly-2 layer is applied above the dummy bitline on the field oxide region wherein the utilization of the field oxide region for placement of the dummy bitline provides a uniform surface between an actual bitline and the periphery of the memory array. Furthermore, a landing pad is formed at the end of the dummy bitline on the field oxide region, wherein the dummy bitline does not cause erroneous operation of the landing pad.

REFERENCES:
patent: 5789313 (1998-08-01), Lee
patent: 5946563 (1999-08-01), Uehara et al.
patent: 6717267 (2004-04-01), Kunikiyo
patent: 2002/0050655 (2002-05-01), Travis et al.
patent: 2003/0015742 (2003-01-01), Ogawa et al.

Affiliated with

Also associated with

Rating

Method and system for improving the topography of a memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for improving the topography of a memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for improving the topography of a memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3864695