Method and system for implementing a cache coherency mechanism f

Details Method and system for implementing a cache coherency mechanism f Method and system for implementing a cache coherency mechanism f

1997-03-05

1998-07-28

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711122, 711144, 711130, 711163, G06F 1200

Patent

active

057874786

ABSTRACT:
A method and system of implementing a cache coherency mechanism for supporting a non-inclusive cache memory hierarchy within a data processing system is disclosed. In accordance with the method and system of the invention, the memory hierarchy includes a primary cache memory, a secondary cache memory, and a main memory. The primary cache memory and the secondary cache memory are non-inclusive. Further, a first state bit and a second state bit are provided within the primary cache, in association with each cache line of the primary cache. As a preferred embodiment, the first state bit is set only if a corresponding cache line in the primary cache memory has been modified under a write-through mode, while the second state bit is set only if a corresponding cache line also exists in the secondary cache memory. As such, the cache coherency between the primary cache memory and the secondary cache memory can be maintained by utilizing the first state bit and the second state bit in the primary cache memory.

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patent: 5428761 (1995-06-01), Herlihy et al.
patent: 5564035 (1996-10-01), Lai
patent: 5636365 (1997-06-01), Tanioka
MIPS Technologies, Inc. Chapter. 11, The R4400 Microprocessor User's Manual, Mar. 21, 1996.

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