Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-01-03
2010-11-02
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07827516
ABSTRACT:
A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit.
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Hersan Thiago
Kheterpal Veerbhan
Moe Matthew D.
Motiani Dipti
Pileggi Lawrence T.
Dimyan Magid Y
PDF Solutions, Inc.
Pillsbury Winthrop et al
Whitmore Stacy A
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