Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2011-06-14
2011-06-14
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
Reexamination Certificate
active
07962886
ABSTRACT:
A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.
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Glusman Marcelo
Hsieh Yee-Wing
Krstic Angela
Lin Andy
Pandey Manish
Cadence Design Systems Inc.
Lin Aric
Siek Vuthe
Vista IP Law Group LLP
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