Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-03-06
2004-05-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S262000, C438S585000
Reexamination Certificate
active
06737325
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacturing and more particularly to a method and system for forming a transistor having source and drain extensions.
BACKGROUND OF THE INVENTION
Transistors are prevalent in today's society. Many challenges exist in creating smaller and faster transistors. One example of a transistor utilizes a source and drain together with source and drain extensions extending under the channel region of the transistor. The source and drain regions as well as the extensions are often formed through an implant and an anneal process. Annealing drives the implanted dopants both downward and laterally, forming the source and drain regions as well as the extensions. Problems occur in accurately defining the source and drain regions and their extensions due to incomplete control of the annealing process.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a method for manufacturing a transistor is provided. The method includes masking a polysilicon layer of a semiconductor device to have a dimension greater than a critical dimension of a gate to be formed. The polysilicon layer overlies a substrate layer. The method also includes incompletely etching the polysilicon layer. The method also includes forming a source region and a drain region in the substrate layer through the incompletely etched polysilicon layer by doping the substrate layer and applying heat at a first temperature. The method also includes forming a source extension and a drain extension in the substrate layer after forming the source region and the drain region by doping the substrate layer and applying heat at a second temperature.
Some embodiments of the invention provide numerous technical advantages. Some embodiments may benefit from some, none, or all of these advantages. For example, according to one embodiment, a shallow junction may be formed for a semiconductor device. In another embodiment, source and drain over-extension may be avoided. In another embodiment, the thermal budget for manufacturing a transistor having source and drain extensions may be reduced.
Other technical advantages may be readily ascertained by one of skill in the art.
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Laaksonen Reima Tapani
Mehrotra Manoj
Brady III Wade James
Lindsay Jr. Walter L.
Niebling John F.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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