Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-04
2010-02-09
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
07661050
ABSTRACT:
The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.
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Huben Gary Van
Seigler Adrian E.
Campbell John E.
Ellis Kevin L
Gandhi Dipakkumar
International Business Machines - Corporation
Jones II Graham S.
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